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ADVANCE INFORMATION
MICRONAS
DDP 3315C Display and Deflection Processor
Edition Dec. 5, 2001 6251-521-1AI
MICRONAS
DDP 3315C
Contents Page 4 5 5 6 6 6 6 8 8 8 10 10 10 11 11 11 12 12 12 13 13 14 14 14 16 16 16 16 18 18 19 19 20 20 20 21 21 21 22 22 22 26 40 Section 1. 1.1. 1.2. 2. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.1.5. 2.1.6. 2.1.6.1. 2.1.6.2. 2.1.7. 2.1.8. 2.1.9. 2.1.10. 2.1.11. 2.1.12. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.3. 2.3.1. 2.3.2. 2.3.3. 2.3.4. 2.3.5. 2.3.6. 2.3.7. 2.3.8. 2.3.9. 2.3.10. 2.3.11. 2.3.12. 3. 3.1. 3.2. 3.3. 3.3.1. Title Introduction System Architecture System Application Functional Description Display Part Digital Input Interface Chroma Input Horizontal Scaler Luma Contrast and Brightness Black Level Expander/Compressor (BLEC) Luma Sharpness Enhancer (LSE) Dynamic Peaking Luma Transient Improvement (LTI) Chroma Interpolation Chroma Transient Improvement Inverse Matrix and Digital RGB Processing Picture Frame Generator Scan Velocity Modulation Non-linear Colorspace Enhancer (NCE) Analog Back End Analog RGB Insertion Fast Blank Monitor Half Contrast Control CRT Measurement and Control Average Beam Current Limiter Synchronization and Deflection Deflection Processing Security Unit for H-Drive Horizontal Phase Adjustment Vertical Synchronization Vertical and East/West Deflection Vertical Zoom EHT Compensation Protection Circuitry Display Frequency Doubling General Purpose D/A Converter Clock and Reset Reset and Power-On Serial Interface I2C-Bus Interface I2C Control and Status Registers XDFP Control and Status Registers Scaler Adjustment
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DDP 3315C
Contents, continued Page 41 41 41 44 47 48 50 50 50 51 52 52 52 53 53 54 55 55 55 55 56 56 56 56 57 58 60 60 61 62 Section 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.4. 4.6.4.1. 4.6.4.2. 4.6.4.3. 4.6.4.4. 4.6.4.5. 4.6.4.6. 4.6.4.7. 4.6.4.8. 4.6.4.9. 4.6.4.10. 4.6.4.11. 4.6.4.12. 4.6.4.13. 4.6.4.14. 4.6.4.15. 4.6.4.16. 4.6.4.17. 5. 6. Title Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Recommended Crystal Characteristics Characteristics General Characteristics LLC2: Line-locked Clock Input Luma, Chroma Inputs Digital Inputs, Static Pins I2C-Bus Interface Horizontal Flyback Input Sync Signals and PWM Outputs Horizontal Drive Output Vertical Protection Input Horizontal Safety Input Vertical and East/West D/A Converter Output East/West PWM Output Sense A/D Converter Input Analog RGB / YPBPR and FB Inputs Analog RGB Outputs, D/A Converters Scan Velocity Modulation Output DAC Reference, Beam Current Safety Application Circuit Data Sheet History
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DDP 3315C Display and Deflection Processor 1. Introduction Deflection Processing The DDP 3315C is a mixed-signal single-chip digital display and deflection processor, designed for highquality backend applications in double scan and HDTV TV sets with 4:3 or 16:9 picture tubes. The interfaces qualify the IC to be combined with state of the art digital scan rate converters, as well as analog HDTV sources. The DDP 3315C contains the entire digital video component, deflection processing, and all analog interfaces to display the picture on a CRT. The main features are Video Processing - linear horizontal scaling (0.25 ... 4), as well as nonlinear horizontal scaling "panorama vision" - dynamic black level expander - luma sharpness enhancement by dynamic peaking and luma transient improvement (LTI) - color transient improvement (CTI) - programmable RGB matrix - black stretch, blue stretch, gamma correction via programmable Non-linear Colorspace Enhancer (NCE) on RGB - two analog double scan inputs with fast blank (one RGB and one RGB/YCrCb/YPrPb selectable)
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- average and peak beam current limiter - automatic picture tube adjustment (cutoff, drive)
- scan velocity modulation output - digital EHT compensation for vertical / east-west - vertical angle and bow correction - differential vertical outputs - vertical zoom via deflection adjustment - horizontal and vertical protection circuit - horizontal frequency for VGA/SVGA/1080I - black switch off procedure - supports horizontal and vertical dynamic focus Miscellaneous - selectable ITU-R 601 4:1:1 / 4:2:2 YCrCb input at 27/32 MHz or double scan ITU-R 656 input at 54 MHz line-locked clock - crystal oscillator for horizontal safety - picture frame generator - hardware for simple 50/60 Hz to 100/120 Hz conversion (display frequency doubling) - PQFP80 package, 5 V analog and 3.3 V digital supply
SVM LLC 27/32/ 54 MHz Y/ 656 YCrCb CrCb 4:2:2 / 4:1:1 SDA SCL Clock Generator Y Input Cb Interface Cr Y Y UpconPicture Cb C version / Improve- b Cr Cr scaling ment
R G B FBL
SVM R G B
analog RGBMatrix R G B R Video G DAC B R Analog G RGB Switch B
Pr Y Pb Input FBL R G B
R Matrix / G PFG / B NCE
Tube Control
Output Sense Input
I2C Interface general purpose PWM
EHT V H
V
Sawtooth / V Parabola EW Generation H-Drive Generation H
V EW H/V dynamic focus
H&V
VERT+ VERT- E/W
Sync Processing
DisplayH Freq. Doubling
H
Security E/W Unit
HOUT
PWM 1/2
2H / 2V (1H / 1V)
FIFO Controlling
HFLB
DFVBL PWMV
VPROT HSAFETY
Fig. 1-1: Block diagram of the DDP 3315C
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play (OSD). The second input is processed with an analog RGB matrix to insert YCbCr/YPbPr or RGB with control of color saturation and programmable half contrast. The bandwidth of ~30 MHz guarantees pixel based graphics to be displayed with full accuracy. All previously mentioned features are implemented in dedicated hardware. An integrated processor controls the horizontal and vertical deflection, tube measurement loops and beam current limitation. It is also used to calculate an amplitude histogram of the displayed image. The horizontal deflection is synchronized with two numeric phase-locked loops (PLL) to the incoming sync. One PLL generates the horizontal timing signals, e.g. blanking and key-clamping. The second PLL adjusts the phase of the horizontal drive pulse with a subpixel accuracy less than 1 ns. Vertical deflection and east/west correction waveforms are calculated as 6th order polynomials. This allows adjustment of an east/west parabola with trapezoidal, pincushion and an upper/lower corner correction (even for real flat CRT's), as well as a vertical sawtooth with linearity and S-correction. Scaling both waveforms, and limiting to fix amplitudes, performs a vertical zoom or compression of the displayed image. A field and line frequent control loop compensates picture content depending EHT distortions.
1.1. System Architecture Fig. 1-1 shows the block diagram of the DDP 3315C. A clock generator converts different external line locked clock rates to a common internal sample rate of ~40 MHz, in order to provide a higher horizontal resolution. The input interface accepts ITU-R 601 at 27 or 32 MHz and ITU-R 656 with encoded or external sync at 54 MHz. The horizontal scaler is used for the scan rate conversion and for the nonlinear aspect ratio conversion as well. For the picture improvement, luma and chroma are processed separately. The luminance contrast ratio can be extended with a dynamic black level expander. In addition the frequency characteristic is improved by a transient improvement (LTI) and an adaptive dynamic peaking circuit. The peaking adapts to small AC amplitudes of high frequency parts, while large AC amplitudes are processed by the LTI. The chroma signal is enhanced with a transient improvement (CTI) with proper limitation to avoid wrong colors. The full programmable RGB matrix covers control of color saturation and temperature. A digital white drive control is used to adjust the white balance and for the beam current limitation to prevent the CRT from overload. A non-linear colorspace enhancer (NCE) for RGB gives full flexibility for any amplitude characteristic. High speed10-bit D/A converters are used to convert digital RGB to analog signals. Separate 9-bit D/A converters control brightness and cutoff. For picture tubes equipped with an appropriate yoke a scan velocity modulation (SVM) signal is calculated using a differentiated luminance signal. Two analog sources can be inserted in the main RGB, controlled by separate fastblank (FBL) signals. Contrast and brightness are adjusted separately from main RGB. One input is dedicated to RGB for on screen dis-
1.2. System Application To form a complete TV set, the video backend must be complemented with additional components. Due to the flexible architecture of the DDP, it can be placed in various environments (see Fig. 1-2). Applications to display digital MPEG or PC graphics on large screens, inserting analog VGA sources in a TV as well as memory based image processing for 100/120 Hz or progressive scan rate conversion of TV sources, are intended with the DDP. Scan Vel. Mod for VGA Motion compensation
CVBS CVBS RGB
VPC 323xD VPC 323xD SDA 9400/1 DDP 3315C RGB H/V Defl. RGB H/V Defl.
OSD, VGA, 1080l CVBS RGB / VGA OSD, 1080l Fig. 1-2: DDP 3315C applications VSP 940x DDP 3315C

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Progressive scan
Line flicker reduction
Combfilter
16:9 Video
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2. Functional Description 2.1. Display Part The display part converts the digital YCrCb to analog RGB (see Fig. 2-1). In case of YCrCb 4:1:1 an interpolation converts the digital input signal to YCrCb 4:2:2 standard format. The 4:2:2 YCrCb signal is processed by the horizontal scaler. In the luminance processing path, contrast and brightness adjustments and a variety of features, such as black level expander and luma sharpness enhancer, are provided. In the chrominance path, the CrCb signals are converted to 4:4:4 format and filtered by a color transient improvement circuit. The YCrCb signals are converted by a programmable matrix to RGB color space.
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Table 2-1: 4:1:1 chroma format Pin Name 1 C7 C6 C5 C4 Cb17 Cb16 Cr17 Cr16 Pixel Number 2 Cb15 Cb14 Cr15 Cr14 3 Cb13 Cb12 Cr13 Cr12 4 Cb11 Cb10 Cr11 Cr10
Table 2-2: 4:2:2 chroma format 2.1.1. Digital Input Interface The digital input interface supports - 16 bit 4:2:2 YCrCb with separate H/V-syncs and clock (ITU-R-601 format) - 12 bit 4:1:1 YCrCb with separate H/V-syncs and clock (ITU-R-601 format) - 8 bit 4:2:2 YCrCb multiplexed with encoded or separate H/V-syncs and clock (ITU-R-656 format) The data inputs Y0...Y7 and C0...C7 are clocked with the external clock LLC2. The clock frequency is selectable between 27 or 32 MHz for 12 and 16 bit data input and 54 MHz for 8 bit data input. The horizontal sync pulse at the HS pin should be an active video signal, which is not vertically blanked. A clock generator converts the different external line locked clock rates to a common internal sample rate of approximately 40.5 MHz, in order to provide a fix bandwidth for all digital filters. Therefore the input data is sample rate converted to the common processing frequency by the horizontal scaler. Pin Name 1 C7 C6 C5 C4 C3 C2 C1 C0 Cb17 Cb16 Cb15 Cb14 Cb13 Cb12 Cb11 Cb10 Pixel Number 2 Cr17 Cr16 Cr15 Cr14 Cr13 Cr12 Cr11 Cr10 3 Cb37 Cb36 Cb35 Cb34 Cb33 Cb32 Cb31 Cb30 4 Cr37 Cr36 Cr35 Cr34 Cr33 Cr32 Cr31 Cr30
Note: Cxy; x = pixel number; y = bit number
2.1.2. Chroma Input The chroma input signal can either be YCrCb in 4:1:1 or in 4:2:2 format. For the digital signal processing the time-multiplexed chroma samples will be demultiplexed, synchronized with the signal at the HS Pin. The input formatter accepts either two's complement or binary offset code. Also the delay can be adjusted within a range of 2 input clocks relative to the luma signal; this doesn't effect the chroma multiplex.
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Fig. 2-1: Detailed block diagram
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27/32/54 MHz
27/32 MHz contrast
40.5/40.0 MHz dig. bright. peaking LTI CTI Y digital R, G, B RGB matrix Cb Cr picture frame gen.
digital / analog scan. vel. mod.
DAC
SVM
CrCb 4:2:2/ 4:1:1
ipl. 4:2:2 Cr Cb
non linear scaler
BLE
Y ipl. 4:4:4 Cb Cr
white-dr. x bcl 3 x NEC
Y LLC2 HS/VS/ VS2 656 interface clock generator
H&V timing 3 x DAC int. bright. x white-dr. 3 x DAC ext. bright. x white-dr. R, G, B
3 x DAC RGB R, G, B 3x DAC cutoff 3x DAC black RGB out FBL Prio FB1/2 in
H/V sync FIFO read ctrl FIFO write ctrl SDA/ SCL int. H/V display frequency doubling XDFP
- H-PLL2/3, flyback control and soft start/stop - vertical, e/w deflection with EHT compensation - beam current limiter - histogram calculation - cutoff & drive control loop - horizontal & vertical protection incl. BSO - dynamic focus
I2C interface
PWM1 PWM2 5 MHz CLK
2 x 8-bit PWM clk security H-drive gen.
H/V protection measurement ADC
3 x VCC ext. contr. x white-dr. x bcl analog RGB matrix
clamping
RGB1 in RGB2/ YCrCb in
DDP 3315C
PWM & Pulse
H-flyb. skew
2 x DAC V, E/W
clamping
HDrive H/V prot. DVBL PWMV H-Flyb
V & E/W sense RSW 1&2
DDP 3315C
2.1.3. Horizontal Scaler The horizontal scaler supports linear or nonlinear horizontal scaling of the digital input video signal in the range of 0.25 to 4. Nonlinear scaling, also called "panorama vision", provides a geometrical distortion of the input picture. It is used to fit a picture with 4:3 format on a 16:9 screen by stretching the picture geometry at the borders. Also, the inverse effect can be produced by the scaler. A summary of scaler modes is given in Table 2-3. Table 2-3: Scaler modes Mode Panorama 4:3 16:9 Panorama 4:3 4:3 Scale Factor non linear compr. non linear zoom Description 4:3 source displayed on a16:9 tube, borders distorted Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan, borders distorted, no cropping sample rate conversion from external to internal pixel clock sample rate conversion from external to internal pixel clock
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2.1.5. Black Level Expander/Compressor (BLEC) The black level expander/compressor modifies the luminance signal with an adjustable non-linear function to enhance the contrast of the picture (see Fig. 2-2). Dark areas are stretched to black, while bright areas remain unchanged. Advantageously, this black level processing is performed dynamically and only if it will be most noticeable to the viewer. The BLEC supports the following modes (see Fig. 2-3): - dynamic BLEC mode This is the normal operation mode. The expansion depends on a pixel analysis. - auto contrast mode In the auto contrast mode, the TILT point is shifted to its maximum. - static BLEC mode In the static mode, the expansion depends on a programmable value SBLE.
Luma out
27 40.5 MHz
1.5 linear 1.25 linear
32 40 MHz
Luma in 2.1.4. Luma Contrast and Brightness The luminance signal is multiplied by a factor of 0...2 in 64 steps. Simultaneously the matrix coefficients are adapted to preserve the color saturation (see Section 2.1.9. on page 11) With a contrast adjustment of 32 (gain=1) the signal can be shifted by 100% of its maximal amplitude with the digital brightness value. This is for adjustment of the headrooms for under- and overshoot. After the brightness addition, the negative going signals are limited to zero. It is desirable to keep a small positive offset with the signal to prevent undershoots produced by the peaking from being cut. Fig. 2-2: BLEC function
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Lout
TILT
compression
expansion BLEGAIN
BRF BLEGAIN
}
TILT BRF X (picture dependant)
subblack region
Lin
Dynamic BLEC mode
TILT
Lout
compression expansion
BRF BLEGAIN BRF X (picture dependant)
}
subblack region
TILT (max of range)
Lin
Autocontrast mode
Lout
TILT
compression expansion BLEGAIN BRF BLEGAIN BRF SBLE TILT
}
(static value)
subblack region
Lin
Static BLEC mode Fig. 2-3: BLEC modes
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2.1.6. Luma Sharpness Enhancer (LSE) Sharpness is one of the most critical features for optimum picture quality. This important processing is performed in the LSE circuitry of DDP 3315C. It consists of the dynamic peaking, the luma transient improvement (LTI) and an adaptive mixer. The luma input signal is processed in the peaking and LTI block in parallel. Both output signals are combined in the mixer depending on the selected LSE characteristic.
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The peaking features two selectable center frequencies of 2.5 MHz or 3.2 MHz (see Fig. 2-5). An adjustable coring threshold prevents the enhancement of small noise amplitudes.
2.1.6.2. Luma Transient Improvement (LTI) For small detail amplitudes the dynamic peaking is the most appropriate processing to improve the sharpness. However, for large amplitudes even small overand/or undershoots of the peaking are too annoying. The luma transient improvement enhances the slope of picture detail without these effects by a non-linear processing. The contour correction signal calculated in this block, is limited to the adjacent extreme values to prevent over- and undershoots (see Fig. 2-7). The LTI features an adjustable gain control and an adjustable coring threshold to prevent the enhancement of small noise amplitudes. The contour correction signals of the dynamic peaking and the LTI block are combined adaptively to achieve best sharpness impression.
2.1.6.1. Dynamic Peaking The dynamic peaking improves the details of a picture by contour emphasis. It adapts to the amplitude and the frequency of the input signal. Small detail amplitudes are sharpened, while large detail amplitudes stay nearly unmodified. The max. dynamic range of small high-frequency detail amplitudes is 14 dB. The dynamic range of large detail amplitudes is limited automatically by a non-linear function that does not create any visible alias components (see Fig. 2-4).
20 15 10 5 0
dB
-5 -10 -15 -20
0 2 4 6 8 10
MHz
Fig. 2-4: Dynamic peaking frequency response
20 15 10 5 0
dB CF = 3.2 MHz S-VHS
20 15 10 5 0
dB CF = 2.5 MHz
-5 -10 -15 -20
0 2 4 6 8 10
-5 -10 -15
MHz
-20
0
2
4
6
8
10
MHz
Fig. 2-5: Dynamic peaking frequency response in S-VHS (all frequencies refers to a 50/60 Hz video signal)
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2.1.7. Chroma Interpolation In case of YCrCb 4:1:1 input format, the digital input signal is converted to 4:2:2 format by an interpolation filter working at the input pixel clock frequency. The signal is passed to the scaler in YCrCb 4:2:2 format, in order to convert the incoming pixel clock frequency (27/32 MHz) to the internal frequency (40.5/ 40 MHz). A linear phase interpolator is used to convert the chroma sampling rate from 4:2:2 to 4:4:4. The frequency response of the interpolator is shown in Fig. 2-6. All further processing is carried out at the full sampling rate. a) C rC b input
b) Ampl.
t
t 0 dB c) Cr out Cb out
-10 -20 -30 -40 -50
0 4 8 12 16 20 MHz
a) CrCb input of CTI b) CrCb input + correction signal c) sharpened and limited CrCb Fig. 2-7: Luma/chroma transient improvement
t
Fig. 2-6: Frequency response of the chroma 4:2:2 to 4:4:4 interpolation filter 2.1.9. Inverse Matrix and Digital RGB Processing 2.1.8. Chroma Transient Improvement The intention of this block is to enhance the chroma resolution. A correction signal is calculated by differentiation of the color difference signals. The differentiation can be selected according to the signal bandwidth, e.g. for PAL/NTSC/SECAM or digital component signals, respectively. The amplitude of the correction signal is adjustable. Small noise amplitudes in the correction signal are suppressed by an adjustable coring circuit. To eliminate "wrong colors", which are caused by over and undershoots at the chroma transition, the sharpened chroma signals are limited to a proper value automatically (see Fig. 2-7). Six multipliers in parallel perform the matrix multiplication to transform the Cr and Cb signals to R-Y, B-Y, and G-Y. The initialization values for the matrix are computed from the standard ITU-R matrix:
R 1 0 1,402 Y G = 1 - 0,345 - 0,713 x Cb B 1 1,773 0 Cr
The multipliers are also used to adjust color saturation and picture contrast. The matrix computes:
R G= B
1 Cb + CTM x Y CTM SATM x ----- x ----------------------- x --------------- 64 MG1M MG2M x 32 32 Cr 32 MB1M MB2M
MR1M MR2M
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2.1.10. Picture Frame Generator The picture frame generator produces a programmable border surrounding the displayed image. By swapping the start and stop parameters a windows is produced instead. The color of the complete border is stored in a programmable frame register. The format is 3x4 bit RGB. The contrast can be adjusted separately.
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2.1.12. Non-linear Colorspace Enhancer (NCE) This block allows all kinds of non-linear functions such as gamma correction, blue stretch, peak white limitation, for each path R,G and B separately. In the following only one path is described (see Fig. 2-9). Whereas the full input range of the NCE is 0...2047, the non-linear function is a combination of 8 I2C programmable linear segments S0 to S7 lying in the range 0...1023. Beyond 1023, the non-linear curve consists of the continuation of S7 and the limitation to 1023. If the segments S0 to S7 cover the full input range from 0 to 1023 they can be placed on a grid of 32. In the case where all segments lie in a smaller range, the following modes with higher precision are available.
2.1.11. Scan Velocity Modulation Picture tubes equipped with an appropriate yoke can use the Scan Velocity Modulation signal to vary the speed of the electron gun during the entire video scan line dependent upon its content. Transitions from dark to bright will first speed up and then slow down the scan; vice versa for the opposite transition (see Fig. 2-8). The signal delay is adjustable by 3.5 clocks in halfclock steps in respect to the analog RGB output signals. This is useful to match the different groupdelay of analog RGB amplifiers to the one for the SVM yoke current.
Table 2-4: Input range and grid covered by S0...S7 Mode XSEG = 0 XSEG = 1 XSEG = 2 XSEG = 3 Range 0...1023 0...511 0...255 0...127 Grid 32 16 8 4
ampl. beam current
XSEG = 3 XSEG = 2
XSEG = 1
SVM yoke current
1023
t Fig. 2-8: SVM signal waveform 0 1024 2047
Fig. 2-9: NCE characteristic
12
XSEG = 0
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2.2. Analog Back End FBFOH1 The digital RGB signals are converted to analog RGB by three 10-bit digital to analog converters (DAC). Each RGB signal has two additional DACs with 9-bit resolution to adjust analog brightness (40% of the full RGB range) and cutoff / black level (60% of the full RGB range). An additional fixed current is applied for the blanking level. The back-end supports the insertion of two external analog component signals, e. g. OSD or analog HDTV. These signals are clamped, processed in an analog matrix (RGB2), converted by a voltage/current converter (VCC), and inserted into the main RGB by the fast blank switch. The analog RGB outputs are current outputs with current-sink characteristics. The maximum current drawn by the output stage is obtained with peak white RGB. The controlling of the whitedrive/analog brightness and also the external contrast and brightness adjustments is done via the internal Processor. FBLIN1 Fast Blank Monitor FBLIN2 # # FB Fast int Blank Selection FBFOL1 FBPOL FBPRIO
FBFOH2 FBFOL2 FBMON Fig. 2-10: Fast Blank selection logic
2.2.1. Analog RGB Insertion The DDP 3315C supports the insertion of - 2 external analog RGB signals or - 1 external analog RGB and 1 external YCrCb/YPrPb signal. Each component signal is clamped, converted to RGB if required, and inserted into the main RGB by the fast blank switch. The external component signals are adjustable independently as regards DC level (brightness) and magnitude (contrast). The second external analog input is processed by an analog matrix with control of color saturation and programmable half contrast.
Over-/underlay of the external component signal and the main RGB signal depends on the fast blank input signals and the corresponding I2C-register (see Fig. 2-10). Both fast blank inputs must be either active low or active high. All signals for analog component insertion (RIN1/2, GIN1/2, BIN1/2, FBLIN1/2, HCS) must be synchronized to the digital RGB. External YCrCb/YPrPb signals are converted to RGB by the following matrix. Table 2-5: Matrix coefficients for 480P and 1080I
1 0 Krr Y R G = 1 K gb K gr C b B Cr 1 K bb 0 I2C Setting MATType Standard Krr Kgb Kgr Kbb 010 ITU-R 601 / 480P (SMPTE 293M) 1.402 -0.344 -0.7144 1.773 100 001
1080I RGB (ITU-R709) (Bypass) 1.575 -0.187 -0.468 1.856 0 0 0 0
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2.2.2. Fast Blank Monitor The presence of external analog RGB sources can be detected by means of a fast blank monitor. The status of the selected fast blank input can be monitored via an I2C register. There is a 2 bit information, giving static and dynamic indication of a fast blank signal. The static bit is directly reading the fast blank input line, whereas the dynamic bit is reading the status of a flip flop triggered by the negative edge of the fast blank signal. With this monitor logic it is possible to detect if there is an external RGB source active and if it is a full screen insertion or only a box. The monitor logic is connected directly to the FBLIN1 or FBLIN2 pin. Selection is done via I2C register.
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2.2.4. CRT Measurement and Control In order to define accurate color on different CRT displays, the cut-off and white drive settings have to be adjusted depending on the characteristic of CRT phosphor. To guarantee correct colors during the for the lifetime of the display, a build in automatic tube control loop measures and adjusts the black level on every field and white point every third field. The display processor is equipped with an 9/12-bit PDM-ADC for all picture tube measuring purposes. This MADC is connected to the SENSE input pin, the input range is 0 to 2.6 V. Cutoff and white drive current measurement are carried out with 8-bit resolution during the vertical blanking interval. The current range for cutoff measurement is set by connecting the sense resistor R1 to the SENSE input. Due to the fact of a 1:10 relation between cutoff and white drive current the range select 2 output (RSW2) becomes active for the white drive measurement and connects R3 in parallel to R1, thus determining the correct current range. During the active picture, the MADC is used for the average beam current limiter with a 12-bit resolution. Again a different measurement range is selected with active range select 1&2 outputs (RSW1&RSW2) connecting R2 in parallel to R3 and R1. See Fig. 2-12 and Fig. 2-13 for the corresponding timing. These measurements are typically done at the summation point of the picture tube cathode currents.
2.2.3. Half Contrast Control Insertion of transparent text pages or OSD onto the video picture is often difficult to read, especially if the video contrast is high. The DDP 3315C features a contrast reduction of the video background of 30 or 50% by means of a half contrast input (HCS pin). This input can be supplied with a fast switching signal (similar to the fast blank input), typically defining a rectangular box. Inside this box the video picture is displayed with reduced contrast, while the analog component signals are still displayed with full contrast.
HCSPOL Another method uses two different current measurements: HCS # HCS intern - The range switch 1 pin (RSW1) can be used as a second sense input, selectable by software. In this case, the cutoff and white drive currents are measured as before at the SENSE input. - The active picture measurement can be done with the second sense input (RSW1). The signal may come (via a proper interface) from the low end of the EHT coil (CRT anode current). In this case, the resistor R2 in Fig. 2-12 has to be removed. The picture tube measurement returns results on every field for: - cutoff R - cutoff G - cutoff B - white drive R or G or B (sequentially)
HCSEN
HCSFOH
Fig. 2-11: Half Contrast switch logic
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DDP 3315C
- If the automatic mode was once enabled (CUT(WDR)_GAIN > 0), the control loop can be stopped by setting CUT(WDR)_DIS = 1. In this mode the calculated cutoff and drive values will no longer be modified and the measurement lines are suppressed. Changes of the reference values (CUT(WDR)_R/G/B) have no effect. If one of the calculated red, green or blue white drive values exceeds it's maximal possible value (WDR_R/ G/B>511), the white balance gets misadjusted. An automatic drive saturation avoidance prevents from this effect (WDR_SAT = 1). If one drive value exceeds the maximum allowed threshold (MAX_WDR) the amplitude of the white drive measurement line will be increased and decreased if one of them goes below the fixed threshold 475.
Thus a cutoff control cycle for RGB requires one field only, while a complete white drive control cycle requires three fields. During cutoff and whitedrive measurement, the average beam current limiter function (see Section 2.2.5.) is switched off. The amplitude of the cutoff and white drive measurement lines can be programmed separately with IBRM and WDRM (see Fig. 2-13). The start line for the tube measurement (cutoff red) can be programmed via I2C-bus (TML). The built-in control loop for cutoff and white drive can operate in three different modes selected by CUT(WDR)_GAIN and CUT(WDR)_DIS. - The user control mode is selected by setting CUT(WDR)_GAIN = 0. In this mode the registers CUT(WDR)_R/G/B are used as direct control values for cutoff and drive. If the measurement lines are enabled (CUT(WDR)_DIS = 0) the user can read the measured cutoff & white drive values in the CUTOFF(WDRIVE)_R/G/B registers. An external software can now control the settings of the CUT(WDR)_R/G/B registers. - The automatic mode is selected by setting CUT(WDR)_GAIN > 0 and CUT(WDR)_DIS = 0. In this mode, the registers CUT(WDR)_R/G/B are used as reference for the measured values (CUTOFF(WDRIVE)_R/G/B). The calculated error is used with a small hysteresis (1.5%) to adjust cutoff and drive. The higher the loopgain (CUT(WDR)_GAIN) the smaller the time constant for the adjustment.
beam current 2
beam current 1
D
A
SENSE
MADC RSW1 RSW2
R2 R3
R1
Fig. 2-12: MADC range switch
CUT_R + IBRM + WDRM*WDR CUT_R + IBRM black cutoff R cutoff G cutoff B white drive R
ROUT
ultra black CUT_G + IBRM
GOUT
CUT_B + IBRM
BOUT active resistors measurement Lines
R1||R2||R3 R1 Internal calibration TML
R1||R3 CUTOFF WDR
R1
R1||R2||R3
BCL VBSO
BCL VBST
Fig. 2-13: MADC measurement timing
Micronas
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DDP 3315C
2.2.5. Average Beam Current Limiter The average beam current limiter (BCL) works on both the digital YCrCb input and the inserted analog RGB signals by using either the sense input or the RSW1 input for the beam current measurement. The BCL uses a different filter to average the beam current during the active picture resulting in a 12-bit resolution. The filter bandwidth is approximately 4 kHz. The beam current limiter allows the setting of a threshold current, a gain and an additional time constant. If the beam current is above the threshold, the excess current is low-pass filtered with the according gain and time constant. The result is used to attenuate the RGB outputs by adjusting the white drive multipliers for the internal (digital) RGB signals, and the analog contrast multipliers for the analog RGB inputs, respectively. The lower limit of the attenuator is programmable, thus a minimum contrast can always be set. If the minimum contrast is reached, the brightness will be decreased to a programmable minimum as well. Typical characteristics of the BCL for different loop gains are shown in Fig. 2-14; for this example the tube has been assumed to have square law characteristics.
ADVANCE INFORMATION
2.3. Synchronization and Deflection 2.3.1. Deflection Processing The deflection processing generates the signals for the horizontal and vertical drive (see Fig. 2-15). This block contains two numeric phase-locked loops and a security unit: - PLL2 generates the horizontal and vertical timing, e.g. blanking, clamping and sync signals. Phase and frequency are synchronized by the incoming sync signals. - PLL3 adjusts the phase of the horizontal drive pulse and compensates for the delay of the horizontal output stage. - The security unit observes the H-Drive output signal. With an external 5 MHz reference clock this unit controls the H-drive "off time" and period. In case of an incorrect H-drive signal the security unit generates a free running h-drive signal divided down from the 5 MHz reference clock. The DDP 3315C is able to synchronize to various horizontal frequencies, even VGA frequencies. Supported horizontal input frequencies are listed in Table 2-6.
beam current
5
gain = 0%
2.3.2. Security Unit for H-Drive The security unit observes the H-Drive output signal with an external 5 MHz reference clock. For different horizontal frequencies the security unit uses different ranges to control the H-Drive signal. Selecting a specific horizontal frequency via I2C-Register HFREQ, automatically switches to the corresponding security range. The control ranges are listed in Table 2-6. The window of the control range has to lie within a main control window which is selectable with the FREQSEL input pin. With a low signal at this pin the main control range is 28.8... 34.4 s and with a high signal the main control range is 25.6... 29.2 s. This is to prevent male functions if the horizontal deflection stage is prepared for VGA frequencies. The Horizontal Drive Output can be forced to the high level during Flyback. This means, the falling edge of the drive pulse is earliest possible at the end of the flyback pulse. This function can be enabled via the I2C bus (EFLB).
3 2 1.5
gain = 10% gain = 60% gain = 90%
1 1.5 2
threshold 1
drive
Fig. 2-14: Beam current limiter characteristics: beam current output vs. drive
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Micronas
ADVANCE INFORMATION
DDP 3315C
Table 2-6: Supported horizontal input frequencies Supply Clock (MHz) 27 27 27 27 27 27 32 32 32 32 32 40.5 Pixels per line Supply clk 864 858 800 768 720 712 1024 944 912 852 844 1296 Main clock (in MHz) 40.5 40.5 40.5 40.5 40.5 40.5 40.0 40.0 40.0 40.0 40.0 40.5 Pixels per line Main clk 1296 1287 1200 1152 1080 1068 1280 1180 1140 1065 1055 1296 horiz. freq. (Hz) Minimum HDrive period (in s) 29.60 29.60 28.80 27.80 25.60 25.60 29.60 28.80 27.80 25.60 25.60 29.60 Maximum H-Drive period (in s) 34.40 34.40 30.60 29.20 28.00 28.00 34.40 30.60 29.20 28.00 28.00 34.40 HFREQ (I2C)
31.24968 31.46853 33.750 35.15625 37.500 37.92135 31.24952 33.89776 35.08747 37.55869 37.91469 31.24968
000 010 100 001 101 110 000 100 001 101 110 000
H flyback
PLL3
phase comparator & lowpass DCO horizontal drive generator Security unit
FREQSEL H drive
PWM 12 bit FIFORWR FIFOWR FIFORRD FIFORD HSYNC 1H or 2H
FIFO control
E/W ouput blanking, clamping, etc. E/W correction PDM 15 bit
display timing phase comparator & lowpass
PLL2
sawtooth DCO PDM 15 bit
V+ output V-
VSYNC 1V or 2V
Display Frequency Doubling
2H 2V
vertical reset
clock & control
Fig. 2-15: Deflection processing block diagram
Micronas
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DDP 3315C
2.3.3. Horizontal Phase Adjustment This section describes a simple way to get a correct horizontal frame position and clamp window for analog RGB insertion. 1. For a correct scaler function in panorama/waterglass mode the digital input data should be centered to the active video input signal. 2. The clamping pulse for analog RGB insertion can be adjusted to the pedestal of the input signal with POFS2. 3. The horizontal raster position of the analog inserted RGB1/2 signal can be set to the desired frame position with POFS3. 4. The horizontal position of the digital RGB signal can be shifted to the left and right with NEWLIN. Following values allowed in respect to POFS2: 90 < (POFS2+NEWLIN) - (clk * SFIF) < 580 clk = 3 @ LLC2 = 27 MHz clk = 2,5 @ LLC2 = 32 MHz 5. Now the positioning of horizontal blanking and the picture frame generator can be done.
ADVANCE INFORMATION
2.3.4. Vertical Synchronization The number of lines per field can be adjusted by software (LPFD). This number is used to calculate the vertical raster. The DDP synchronizes only to a vertical sync within a programmable detection window (LPFD VSYNCWIN). If there is no vsync the DDP runs with maximum allowed lines and if the vertical frequency is to high it runs with minimum allowed lines. The smaller the detection window the slower the DDP gets synchronized to the incoming vertical sync. In case of an interlaced input signal it is possible to display both fields at the same raster position by setting R_MODE to 1 or 2. An automatic field length adaptation can be selected (VA_MODE). In this case the vertical raster will be calculated according to the counted number of lines per field instead from LPFD. This is useful for video recorder search mode when the number of lines per field does not comply with the standard, or if you want to use a common value of LPFD for PAL and NTSC (e.g.: LPFD = 290; VSYNCWIN = 54).
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Micronas
ADVANCE INFORMATION
DDP 3315C
2.3.5. Vertical and East/West Deflection
1
Vertical amplitude
The calculations of the Vertical deflection and East/ West correction waveforms are done in the internal processor. They are described as polynomials in x, where x varies from -0.5*zoom to +0.5*zoom for one field. For zoom>1, the range is limited between -0.5 and +0.5. The vertical deflection waveform is calculated as follows (without EHT compensation):
V = vpos + ampl ( x + lin ( x - offset ) + scor x ( x - offset ) )
2 2
0.75 0.5 0.25 0
-0.25 -0.5 -0.75 -1 1
0.75
-0.5 -0.5 -0.3 -0.3 -0.1 -0.1 0.1 0.1 0.3 0.3 0.5 0.5
x
E/W amplitude
defines the vertical raster position is the vertical raster amplitude (zoom 1) - LIN is the linearity coefficient - SCOR is the coefficient for S-correction - OFFSET is an internal parameter The vertical sawtooth signal will be generated from a differential current D/A converter and can drive a DC coupled power stage. In order to get a faster vertical retrace timing, the output current of the vertical D/Aconverter can be increased during the retrace for a programmable number of lines (FLYBL). The range between the end of the flyback and the beginning of the raster is also programmable (HOLDL). The East/West deflection waveform, generated from a single ended D/A converter, is given with the equation:
E W = width + trapez x + cush x + corner x
2 4
- VPOS - AMPL
0.5 0.25
0 -0.25 -0.5 -0.75 -1 -0.5 -0.5
-0.3 -0.3 -0.1 -0.1 0.1 0.1 0.3 0.3 0.5 0.5
x
Fig. 2-16: Vertical and East/West deflection waveforms
2.3.6. Vertical Zoom With vertical zoom the DDP 3315C is able to display different aspect ratios of the source signal on tubes with 4:3 or 16:9 aspect ratio by adapting the corresponding raster.
- - - - -
WIDTH TRAPEZ CUSH CORNU CORNL
is a DC value for the picture width is the trapezoidal correction is the pincushion correction is the upper corner correction is the lower corner correction
vertical sawtooth Start Stop East/West parabola
normal Fig. 2-17: Vertical zoom
zoom
Micronas
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DDP 3315C
2.3.7. EHT Compensation The vertical deflection waveform can be scaled according the average beam current. This is used to compensate the effects of electric high tension changes due to beam current variations. EHT compensation for East/West deflection is done with an offset corresponding to the average beam current. The time constant of this process is free programmable with a resolution of 18 bit. Both corrections can be enabled separately. The maximum scaling coefficient for vertical deflection is 1x and the maximum offset for east/ west is y, where x, y are adjustable from 0 to 0.25. The horizontal phase at the output HOUT can be influenced according to the average beam current in a range of 1.5 s. 2.3.8. Protection Circuitry Picture tube and drive stage protection is provided through the following measurements: - Vertical protection input: this pin watches the vertical sawtooth signal. In every field the sawtooth must descend below the lower threshold A and ascend above the upper threshold B. In this case the protection flag is set (sawtooth o.k.). If an error occurs the protection flag is cleared. After a programmable number of fields with cleared flag the RGB drive signals are blanked. The blanking is cancelled if the flag is set a programmable number of lines (see Fig. 2-18) - Drive shutoff during flyback: this feature can be selected by software (EFLB) - Safety input pin: this pin has two thresholds. The lower threshold A watches for a positive edge in every line, and the upper threshold B must not be overshoot, otherwise the RGB signals are blanked and a soft stop can be performed (HPROT_SS). Both thresholds have a small hysteresis.
ADVANCE INFORMATION
2.3.9. Display Frequency Doubling The DDP 3315C handles single or double vertical and horizontal input frequencies. The display frequency doubling is used when single H/V frequencies are applied and an external FIFO for scan rate conversion is used. In this mode it is mandatory to supply an active video signal to the HS pin, which is not vertical blanked. Three different raster modes are selectable via I2C bus: A A` B` B (normal operation) A A B B (improved vertical resolution) A A B` B` (non interlaced) A/B means field A/B in original raster position and A`/B` means field A/B in the opposite raster position. A minimum field length filter can be switched on (DFDFILT) to write only the smallest field length of the past up to four fields into the memory. This prevents read before write errors in signals with a strong changing field length (e.g. VCR signals).
vert. protection flag 1 accu -1 ~10 fields blanking t Fig. 2-18: Vertical protection timing ~40 fields
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Micronas
ADVANCE INFORMATION
DDP 3315C
2.3.12. Reset and Power-On The IC provides an internal voltage supervision to generate an internal reset during power on or when the supply voltage goes below a certain level (VSTBY and VSUPD < 2.75 V and/or VSUPO < 4.2 V). Also a clock supervision of the 5 MHz clock keeps the internal reset active until proper clock signal is detected (e.g three clock cycles with the correct period). When the reset Pin RESQ or the internal reset becomes active all counters and registers are set to zero. When the reset pin is released, the internal reset is still active for approximately 4 s. Then all registers are loaded with their default values listed in Table 3-5 on page 29. This initialization takes about 100 s. The HOUT signal becomes high with the VSTBY supply after power-on, regardless of RESQ, VSUPP/D, and VSUPO. When a proper 5 MHz clock is established (e.g. 8 ms after VSTBY is powered up), HOUT outputs a 55 kHz pulse. This state remains until an I2C command starts the self-start procedure (RAMP_EN = 1).
2.3.10. General Purpose D/A Converter There are two D/A converters using pulse width modulation. The resolution is 8 bit and the clock frequency is 20.25 MHz. The outputs are push pull types. For a ripple-free output voltage a first order lowpass filter with a corner frequency < 120 Hz should be applied. The D/A converters are adjusted via the I2C bus. They can be used to generate two DC voltages, for example for horizontal raster position, raster tilt or just as switching outputs, when the values 0 and 255 are selected.
2.3.11. Clock and Reset The DDP 3315C supports 27, 32, 40.5 and 54 MHz line-locked clock rates. This external clock rate is converted internally to a clock rate of 40.5 or 40 MHz by means of a PLL. Selection of external clock frequency is done with Pins CM1 and CM0. See Table 2-7 for clock frequency selection. To ensure lock of PLL a reset pulse of at least 500 s must be applied after power up. Table 2-7: Clock frequency selection 656EN 0 0 0 1 CM1 0 0 1 0 CM0 0 1 0 0 LLC2 27 MHz 32 MHz 40.5 MHz 54 MHz
I2C : RAMP_EN = 1 HOUT VSTBY VSUPP/D/O RESQ ~8 ms Fig. 2-19: Reset timing ~85 ms
Micronas
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DDP 3315C
3. Serial Interface 3.1. I2C-Bus Interface Communication between the DDP 3315C and the external controller is done via I2C-bus. The DDP 3315C has an I2C-bus slave interface and uses I2C clock synchronization to slow down the interface if required. Basically there are two classes of registers in the DDP 3315C. The first class are directly addressable I2C registers. They are embedded in the hardware. These registers are 8 or 16 bits wide. The second class are "XDFP-REGISTERS", which are used by the "XDFP" onchip controller. These registers are all 16 bits wide and support read/write operation. Communication with these registers requires I2C packets with a 16 bit XDFP-register address and 16 bit data. Communication with both classes of registers (I2C and XDFP-REGISTERS) are performed via I2C. The format of the I2C telegram depends on which type of register is being accessed.
ADVANCE INFORMATION
The I2C-bus chip address of the DDP 3315C is given below: Note: The I2C address is subject to change.
A6 1
A5 0
A4 0
A3 0
A2 1
A1 0
A0 1
R/W 1/0
3.2. I2C Control and Status Registers The I2C-bus interface uses one level of subaddress. First the bus address selects the IC, then a subaddress selects one of the internal registers. They have 8 or 16-bit data size; 16-bit registers are accessed by reading/writing two 8-bit data words. Writing is done by sending the device address first followed by the subaddress byte and one or two data bytes. For reading, the read address has to be transmitted first by sending the device write address followed by the subaddress a second start condition with the device read address and reading one or two bytes of data. Fig. 3-2 shows I2C protocol for read and write operations; the read operation requires an extra start condition and repetition of the chip address with read command set. Table 3-2 gives definitions of the I2C control and status registers.
SDA SCL S
1 0
P
S P
= I2C-Bus Start Condition = I2C-Bus Stop Condition
Fig. 3-1: I2C-Bus protocol (MSB first, data must be stable while clock is high)
Write to I2C control register : S 1000 101 W Ack sub-addr. Ack 1 or 2 byte data Ack P
Read from I2C control register : S 1000 101 W Ack sub-addr. Ack S 1000 101 R Ack high byte data Ack low byte data Nak P
W = 0 (Write bit) R = 1 (Read bit)
S = Start condition P = Stop condition
Ack = 0 (Acknowledge bit from DDP = grey or Controller = hatched) Nak = 1 (Not acknowledge bit from Controller = hatched or indicating an error state from DDP = grey)
Fig. 3-2: I2C-Bus protocol
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Micronas
ADVANCE INFORMATION
DDP 3315C
Table 3-1: I2C Register List in Numerical Order Ref. Addr. (hex) 10 11 12 13 14 15 16 17 18 1E 9F Mode Register Name Updated
8-r/w 16-w 16-w 16-w 8-r/w 8-r/w 16-w 16-w 8-w 8-r 16-r
PSTR PFC dfpwr dfprd LUTCTRL PSTRV MINHY ATVTY MCRTL FBLSTAT HW_VER
immediately immediately immediately immediately immediately immediately immediately immediately immediately immediately immediately
Table 3-2: I2C Control and Status Registers in Functional Order
Ref. Addr. (hex) Bit Slice Min. Max. Function Default Register Name
Hardware Version 9F bit[3:0] bit[7:4] bit[15:8] hardware version number minor version number major version number not used XDFP Interface 12 bit[9:0] bit[15:10] 13 bit[9:0] bit[15:10] 0 511 0 0 511 0 XDFP write address 10-bit XDFP RAM address reserved, set to "0" XDFP read address 10-bit XDFP RAM address reserved, set to "0" 0 DFPRD 0 DFPWR 1 2 HW_VER HWVER_MIN HWVER_MAJ
Micronas
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DDP 3315C
Table 3-2: I2C Control and Status Registers in Functional Order, continued
Ref. Addr. (hex) Bit Slice Min. Max. Function
ADVANCE INFORMATION
Default
Register Name
Black Level Expander 17 bit[3:0] bit[5:4] 0 0 15 3 0 3 7 BLE activity control BLE tilt point BLE gain maximum gain minimum gain 10 IRE black offset level (NTSC) reserved, set to "0" 7 noise margin for the activity measurement reserved, set to "0" BLE mode control bit[1:0] 0 3 0 1 2 3 7 BLE mode 0: BLE off 1: autocontrast mode 2: dynamic mode 3: static mode static BLE break point reserved, set to "0" Non-linear Colorspace Enhancer (NCE) 14 bit[1:0] 0 1 2 3 bit[2] bit[3] bit[4] bit[5] bit[7:6] 0 0 0 0 1 1 1 1 NCE configuration register input segment resolution 32 bits per step input range: 0..1023 16 bits per step input range: 0..511 8 bits per step input range: 0..255 4 bits per step input range: 0..127 enables/disables LSB correction enables/disables rounding always y range extension bit bypass reserved, set to "0" Picture Frame Generator 11 bit[3:0] bit[7:4] bit[11:8] bit[15:12] 0 0 0 0 15 15 15 picture frame color, 12-bit wide blue amplitude green amplitude red amplitude reserved, set to "0" 0 0 0 PFC PFCB PFCG PFCR 0 0 0 1 0 LSBCORDIS APWMDIS YEX NLBY 0 LUTCTRL XSEG 2 MCRTL BLEMODE 7 1 ATVTY TILT BLEGAIN
bit[8:6] bit[11:9] bit[14:12] bit[15] 18
0 0 0 0
3 0 1
IRE10
AMPLTHR
bit[4:2] bit[7:5]
0 0
3
SBLE
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Micronas
ADVANCE INFORMATION
DDP 3315C
Table 3-2: I2C Control and Status Registers in Functional Order, continued
Ref. Addr. (hex) Bit Slice Min. Max. Function Default Register Name
Analog Fast Blank Monitor 1E bit[0] bit[1] bit[7:2] 0 0 0 1 1 fast blank signal status FBLIN level low/high FBLIN slope reserved, set to "0" Output Pins 10 bit[1:0] 0 1 2 3 bit[2] bit[3] bit[4] bit[5] bit[6] bit[7] 15 bit[1:0] 0 3 0 3 3 0 3 0 0 0 0 0 0 1 1 1 1 1 1 output pin configuration pin driver strength, FIFO control maximum strength (7) medium strength (5) minimum strength (3) tristated strong/weak (7/3) driver strength PWM1 strong/weak (7/3) driver strength PWM2 strong/weak (7/3) driver strength PWMV disable/enable PWM output for EW Pin high/low active horizontal flyback input strong/weak (7/3) driver strength DFVBL output pin configuration pin driver strength for EW maximum strength (7) minimum strength (4) pin driver strength for H-/V-SYNC maximum strength (7) minimum strength (4) reserved, set to "0" 0 0 0 0 0 0 0 PSTPW1 PSTPW2 PSTPV2 EWPWM FLYPOL PSTDF PSTRV PSTEW 0 PSTR PSTSY FBLSTAT FBLEV FBSLO
bit[3:2]
0
0
PSTHVS
bit[7:4]
0
0
Micronas
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DDP 3315C
3.3. XDFP Control and Status Registers The second class are "XDFP-REGISTERS", which are used by the XDFP onchip controller. Access to these registers is achieved by subaddressing. Writing to these registers is done by sending the device write address first, followed by the XDFP-write subaddress, two address bits for the desired XDFP-register and the two data bytes. For reading, the XDFP-register address has to be transmitted first by sending the device write address, followed by the XDFP-read subaddress and the two XDFP-register address bytes. Without sending a stop condition, reading of the addressed data is done by sending the device read address and reading two bytes of data. Fig. 3-3 shows I2C protocol for read and write operations.Table 3-5 on page 29 gives definitions of the XDFP control and status registers. If these registers are smaller than 16 bit the remaining bits should be 0 on write and read operations. Due to the internal architecture, the IC cannot react immediately to an I2C requests, which interacts with the onchip controller. The maximum response timing is appr. 20 ms. If the addressed controller is not ready for further transmissions on the I2Cbus, the clock line SCL is pulled low. This puts the current transmission into a wait state. After a certain period of time the clock line will be released and the interrupted transmission is carried on.
ADVANCE INFORMATION
Table 3-3: XDFP read/write address XDFP Read address XDFP Write address h'13 h'12
A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of registers with the default values given in Table 3-5 on page 29. The register modes are 8/16r w r/w bit width read only register write only register write/read data register
Note: set unused bits to `0`! The mnemonics used in the Micronas demo software are given in the last column.
Write to XDFP control register:
S 1000101 W Ack XDFP-writeaddr. Ack highbyte addr. Ack lowbyte addr. Ack highbyte data Ack lowbyte data Ack P
Read from XDFP control register:
S 1000101 W Ack XDFP-readaddr. Ack highbyte addr. Ack lowbyte addr. Ack S 1000101 R Ack highbyte data Ack lowbyte data Nak P
W = 0 (Write bit) R = 1 (Read bit)
S = Start condition P = Stop condition
Ack = 0 (Acknowledge bit from DDP = grey or Controller = hatched) Nak = 1 (Not acknowledge bit from Controller = hatched or indicating an error state from DDP = grey)
Fig. 3-3: XDFP protocol
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Micronas
ADVANCE INFORMATION
DDP 3315C
Table 3-4: XDFP Register List in Numerical Order Ref. Addr. (hex) 154 157 158 15A 15B 15C 15F 160 164 167 168 16A 16B 16C 16E 16F 170 171 172 173 174 175 176 178 179 17B 17C 17D 17E 17E 180 181 182 Mode Register Name Updated
Table 3-4: XDFP Register List in Numerical Order Ref. Addr. (hex) 20 59 6B 6C 6D 6E 6F 70 116 117 11F 127 131 132 133 134 135 136 137 138 139 13A 13B 13C 13D 13E 13F 14A 14B 14E 14F 152 153 Mode Register Name Updated
16-r 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w
VER BC CUTOFF_R CUTOFF_G CUTOFF_B WDRIVE_R WDRIVE_G WDRIVE_B AMCTRL RCTRL0 GCTRL0 BCTRL0 SCMODE FFLIM SCINC1 SCINC2 SCINC SCW1_1 SCW1_2 SCW1_3 SCW1_4 SCW1_5 SCW2_1 SCW2_2 SCW2_3 SCW2_4 SCW2_5 LTI SFIF LTIMIX1 BCT LTIMIX2 GCT
immediately immediately vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical
16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w
PFG RCT PBFB1 BRM SVM2 TML SVLIM vbso vbst SVM1 PFGVE PK1 DTICTRL PFGVB PK2 CRCTRL INFMT HDRV NEWLIN HBST HBSO PFGHB PFGHE DFHB DFHE PWM2 PWM1 DFDCTRL PWMV PWMV HCTRL POFS2 POFS3
vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical horizontal horizontal
Micronas
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DDP 3315C
Table 3-4: XDFP Register List in Numerical Order Ref. Addr. (hex) 183 185 187 188 18F 190 191 192 193 194 195 196 197 198 19A 19B 19C 19D 19E 19F 1A0 1A6 1A7 1A8 1A9 1AA 1AB 1AC 1AD 1AF 1B0 1B1 1B2 Mode Register Name Updated
ADVANCE INFORMATION
Table 3-4: XDFP Register List in Numerical Order Ref. Addr. (hex) 1B3 1B4 1C0 1C1 1C2 1C3 1C4 1C5 1C6 1C8 1C9 1CA 1CB 1CF 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1DB 1DC 1DD 1DF 1E2 1E3 1E8 1E9 1EA 1EA 1EB Mode Register Name Updated
16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w
PKP2 PKP3 ANGLE BOW CENTER AMPL ZOOM VPOS LIN SCORR VSYNWIN LPFD HOLDL FLYBL WIDTH TCORR CUSH CRNU CRNL CRNUS CRNLS SATM CTM MB2M MB1M MG2M MG1M MR2M MR1M EHT_THRES EHT_STC EHTV_SA1 EHTV_SA2
horizontal horizontal horizontal horizontal vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical horizontal horizontal horizontal horizontal
16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w
EHTH_SA1 EHTH_SA2 IBRM MADCLAT MCTRL CUT_R CUT_G CUT_B CUT_GAIN WDR_R WDR_G WDR_B MAX_WDR BCL_BRED BCL_GAIN BCL_THRES BCL_TC BCL_TCUP BCL_MIN_C BCL_MIN_B BC_MIN BC_MAX EXT_CONTR EXT_BRT INT_BRT FBLMODE VS_MODE R_MODE VA_MODE WDR_SAT HPROT_SS HSTOP BSO_EN
horizontal horizontal vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical immediately immediately immediately immediately immediately immediately immediately immediately immediately vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical vertical
28
Micronas
ADVANCE INFORMATION
DDP 3315C
Table 3-5: XDFP Control and Status Registers in Functional Order
Ref Addr. (hex) Bit Slice Min. Max. Function Default Register Name
XDFP Status Register 20 bit[7:0] firmware version number firmware release Input Formatter 170 bit[0] bit[1] bit[2] bit[4:3] bit[5] bit[6] 0 0 0 0 0 0 1 1 1 3 1 1 input format 0/1 4:2:2/4:1:1 mode 0/1 binary offset/2` s complement 0/1 enable/disable blanking to black (for luma and chroma input when HS = 0) select color multiplex use HS, VS/VS2 pin instead of embedded 656 sync invert field ID flag Scaler Control Register 131 bit[1:0] 0 1 2 3 bit[13:2] bit[14] bit[15] 132 133 134 135 136 137 138 139 13A 13B 13C 13D bit[11:0] bit[11:0] bit[11:0] bit[11:0] bit[11:0] bit[11:0] bit[11:0] bit[11:0] bit[11:0] bit[11:0] bit[11:0] bit[11:0] 0 0 0 1024 256 0 0 0 0 0 0 0 0 0 1 1 1295 4095 1024 4095 4095 4095 4095 4095 4095 4095 4095 4095 scaler mode register scaler mode linear scaling mode nonlinear scaling mode, 'panorama' nonlinear scaling mode, 'waterglass' reserved reserved, set to "0" 0 scaler update command, set to "1" to update only scaler mode register 0 scaler update command, set to "1" to update all scaler control registers active video length for 1-h FIFO, length in pixels 720 LLC mode (864/h) scaler 1 coefficient, this scaler compresses the signal, compression by a factor "c", the value c*1024 is required scaler 2 coefficient, this scaler expands the signal, expansion by a factor "c", the value 1/c*1024 is required scaler1/2 nonlinear scaling coefficient scaler 1 window register for control of nonlinear scaling scaler 1 window register for control of nonlinear scaling scaler 1 window register for control of nonlinear scaling scaler 1 window register for control of nonlinear scaling scaler 1 window register for control of nonlinear scaling scaler 2 window register for control of nonlinear scaling scaler 2 window register for control of nonlinear scaling scaler 2 window register for control of nonlinear scaling 720 1024 682 0 0 0 0 0 0 0 1 2 SCMODUP SCUPDATE FFLIM SCINC1 SCINC2 SCINC SCW1_1 SCW1_2 SCW1_3 SCW1_4 SCW1_5 SCW2_1 SCW2_2 SCW2_3 0 SCMODE PANO 1 1 1 0 0 0 INFMT M411 COB BLNK CMUX EXTSYNC INVFIELD 0x21 VER FW_REL
Micronas
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DDP 3315C
Table 3-5: XDFP Control and Status Registers in Functional Order, continued
Ref Addr. (hex) 13E 13F Bit Slice Min. Max. Function
ADVANCE INFORMATION
Default
Register Name
bit[11:0] bit[11:0]
0 0
4095 4095
scaler 2 window register for control of nonlinear scaling scaler 2 window register for control of nonlinear scaling Luma Channel
3 4
SCW2_4 SCW2_5
14A bit[3:0] bit[6:4] bit[7] 14E bit[0] bit[5:1] 0 0 1 31 0 0 0 15 7 1
LTI control LTI gain LTI coring peaking/LTI enable LTI mixer control 1 LTI mode amplitude offset to start ampl. adaptive mixing (1 step corresponds to 32 amplitude levels) 0...31 no ...max. offset velocity of mixing 0: fast 3: slow bit[8] 0 1 amplitude adaptive/static mixing LTI mixer control 2 bit[5:0] 0 63 static mixer coefficient 0: 100% peaking 63: 100% LTI bit[8:6] 0 -256 255 reserved, set to "0" luma DC-offset luma peaking filter, the gain at high frequencies and small signal amplitudes is 1 + (k1+k2)/8 bit[3:0] bit[7:4] bit[8] 0 0 0 15 15 1 k1: peaking level undershoot k2: peaking level overshoot peaking value normal/inverted (peaking/softening) luma peaking filter, coring 0 31 coring level peaking reduction 000 001 01X 100 101 11X bit[8] 0 1 100% 80% 60% 50% 40% 30% peaking filter center frequency high/low 0 3 0 4 4 0 0 0 0 0 0 6 4 1 1
LTI LTIGAIN LTICOR LTIEN LTIMIX1 LTIMODE MIXOFFSET
bit[7:6]
0
3
3
MIXGAIN
MIXMODE LTIMIX2 MIXCOEFF
152
15A 16A
bit[8:0]
BRM PK1 PKUN PKOV PKINV PK2 COR PKRD
16E
bit[2:0] bit[4:0] bit[7:5]
PFS
30
Micronas
ADVANCE INFORMATION
DDP 3315C
Table 3-5: XDFP Control and Status Registers in Functional Order, continued
Ref Addr. (hex) Bit Slice Min. Max. Function Default Register Name
Chroma Channel 16B bit[3:0] bit[7:4] bit[8] 16F bit[2:0] bit[3] bit[4] bit[5] -2 0 0 0 1 2 0 0 0 15 15 1 digital transient improvement coring value DTI gain narrow/wide bandwidth mode luma/chroma matching delay variable chroma delay reserved, set to "0" CB (U) sample first / CR (V) sample first reserved, set to "0" Inverse Matrix 1A6 bit[14:9] 0 63 picture saturation in steps of 1/32 picture matrix coefficient B-Y = MB1M/64*CB + MB2M/64*CR 1A8 1A9 bit[15:7] bit[15:7] -64 0 63 127 picture matrix coefficient G-Y = MG1M/64*CB + MG2M/64*CR 1AA 1AB bit[15:7] bit[15:7] -64 -64 63 63 picture matrix coefficient R-Y = MR1M/64*CB + MR2M/64*CR 1AC 1AD bit[15:7] bit[15:7] 0 -64 127 63 Non-Linear Color-Space Enhancer 117 11E bit[8:0] bit[9] bit[14:10] bit[15] 11F 126 bit[8:0] bit[9] bit[14:10] bit[15] -256 0 0 0 -256 0 0 0 31 255 31 255 difference between Y-coordinate of the current basepoint and the linear characteristic reserved, set to "0" X-coordinate of segment basepoint reserved, set to "0" difference between Y-coordinate of the current basepoint and the linear characteristic reserved, set to "0" X-coordinate of segment basepoint reserved, set to"0" 0 0 0 0 0 0 0 0 GX0 GX7 GDY0 GDY7 RX0 RX7 RDY0 RDY7 86 0 MR2M MR1M -44 -22 MG2M MG1M 0 113 MB2M MB1M 32 SATM 0 0 0 ENVU 1 5 1 DTICTRL DTICO DTIGA DTIMO CRCTRL CDEL
Micronas
31
DDP 3315C
Table 3-5: XDFP Control and Status Registers in Functional Order, continued
Ref Addr. (hex) 127 12E Bit Slice Min. Max. Function
ADVANCE INFORMATION
Default
Register Name
bit[8:0] bit[9] bit[14:10] bit[15]
-256 0 0 0
255
difference between Y-coordinate of the current basepoint and the linear characteristic reserved, set to "0"
0 0 0 0
BDY0 BDY7
31
X-coordinate of segment basepoint reserved, set to "0" Picture Frame Generator
BX0 BX7
14F
bit[3:0] bit[7:4]
0 0 13
reserved, set to "0" picture frame contrast B B amplitude = PFCB * (PFBCT + 4) 14,15 invalid reserved, set to "0" picture frame contrast G G amplitude = PFCG * (PFGCT + 4) 14,15 invalid 7 1 picture frame generator priority id enable prio id for picture frame generator reserved, set to "0" picture frame contrast B R amplitude = PFCR * (PFRCT + 4) 14,15 invalid 1 disable/enable analog fast blank input1/2 if bit[x] is set to "1", then the function is active for the respective signal priority vertical picture frame end line vertical picture frame start line (+128) vertically disabled 13 13
0 8 PFBCT
153
bit[3:0] bit[7:4]
0 0
0 8 PFGCT
154
bit[2:0] bit[8]
0 0 0 0
7 0 0 8
PFGID PFGEN
157
bit[3:0] bit[7:4]
PFRCT
158
bit[7:0]
0
0
PBFB1
168 16C 175
bit[8:0] bit[8:0] bit[10:0]
0 1 0
511 511 0 1295
57 0 280
PFGVE PFGVB PFGHB
horizontal picture frame begin (see table for max. pixels per line) 0 horizontally disabled h'7FF full frame 1295 horizontal picture frame end (see table for max. pixels per line)
176
bit[10:0]
0
137
PFGHE
32
Micronas
ADVANCE INFORMATION
DDP 3315C
Table 3-5: XDFP Control and Status Registers in Functional Order, continued
Ref Addr. (hex) Bit Slice Min. Max. Function Default Register Name
Brightness and Contrast 1A7 1DB 1DC bit[14:9] bit[14:6] bit[15:6] 0 0 -256 63 511 255 picture contrast in steps of 1/32 analog contrast for external RGB analog brightness for external RGB The range allows for both increase and reduction of brightness. internal analog brightness The range allows for both increase and reduction of brightness. Scan Velocity Modulation 15B bit[3:0] bit[7:4] bit[8] 15F bit[7:0] bit[8] 167 bit[5:0] bit[8:6] 0 0 63 6 0 0 0 0 0 255 15 15 delay of SVMOUT in steps of 12.5 ns (SVMOUT vs. RGBOUT is 60 ns @7) coring value reserved, set to"0" limit value reserved, set to"0" video mode coefficients gain differentiator delay (0 = filter off) Beam Current Limiter (BCL) 59 1CF 1D0 1D1 1D2 bit[14:3] bit[11:4] bit[14:6] bit[15:3] bit[8:0] 1 1D3 1D4 1D5 1D6 1D7 1DB bit[8:0] bit[14:6] bit[14:6] bit[14:3] bit[14:3] bit[0] 1 0 0 0 0 0 511 511 0 511 511 4095 4095 0 1 0 0 0 0 4095 255 511 beam current, latched every line except during vertical blanking brightness reduction depending on measured BC BCL loopgain 0 0 0 0 0 BC BCL_BRED BCL_GAIN BCL_THRES BCL_TC 60 1 100 0 SVM1 SVG SVD SVLIM 7 0 SVDEL SVCOR 32 360 128 CTM EXT_CONTR EXT_BRT
1DD
bit[15:6]
-256
255
24
INT_BRT
4095 BCL threshold current if sense input used -4096 if RSW1 input used BCL time constant: BCL off 800 ms...0.025 ms second BCL time constant for increasing contrast take BCL_TC instead BCL minimum contrast (= 0..max contrast) BCL minimum brightness (= 0..max bright.) minimum beam current (reset every field) maximum beam current (reset every field) beam current limitation reduces ext. RGB BCL does not reduce ext. RGB
0 0 0 0 0 0
BCL_TCUP BCL_MIN_C BCL_MIN_B BC_MIN BC_MAX NOOSDBCL
Micronas
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DDP 3315C
Table 3-5: XDFP Control and Status Registers in Functional Order, continued
Ref Addr. (hex) Bit Slice Min. Max. Function
ADVANCE INFORMATION
Default
Register Name
Tube Measurement 15C 1C1 1C2 bit[8] bit[9] bit[10] bit[13] bit[14] 0 0 0 0 0 1 0 1 1 1 1 bit[8:0] bit[10:0] 0 0 511 1295 tube measurement linestart line for tube measurement (+2 lines) latch timing of madc data in pixels before the begin of horiz. blanking HBST measurement control word enable/disable ultra black blanking all outputs blanked (video mute) normal mode broad/narrow measurement bandwidth disable/enable horizontal blanking during measurement disable/enable RSW1 pin as input for beam current measurement Cutoff and Drive Measurement 6B 6C 6D 6E 6F 70 146 1C0 1C2 1C2 1C3 1C4 1C5 1C6 bit[11:3] bit[11:3] bit[11:3] bit[11:3] bit[11:3] bit[11:3] bit[8:0] bit[14:6] bit[11] bit[12] bit[12:4] bit[12:4] bit[12:4] bit[14:6] 1 1C7 bit[14:6] 1 1C8 1C9 1CA 1CB 1E9 bit[12:4] bit[12:4] bit[12:4] bit[14:6] bit[0] 0 0 0 475 0 0 0 0 0 0 0 0 0 0 0 0 0 0 511 511 511 511 511 511 511 511 1 1 511 511 511 0 511 0 511 511 511 511 511 1 latched cutoff Red latched cutoff Green latched cutoff Blue latched White Drive Red latched White Drive Green latched White Drive Blue RGB values for white drive beam current measurement internal brightness for measurement. enable/disable white drive measurement enable/disable cutoff measurement reference for cutoff Red reference for cutoff Green reference for cutoff Blue the reference values were taken directly as cutoff values; gain for cutoff control loop the reference values were taken directly as white drive values gain for white drive control loop reference for White Drive Red reference for White Drive Green reference for White Drive Blue threshold for automatic drive saturation avoidance disable/enable automatic drive saturation avoidance 0 WDR_GAIN 0 0 0 0 0 0 0 256 0 0 511 511 511 0 CUTOFF_R CUTOFF_G CUTOFF_B WDRIVE_R WDRIVE_G WDRIVE_B WDRM IBRM WDR_DIS CUT_DIS CUT_R CUT_G CUT_B CUT_GAIN 0 0 0 0 0 10 128 TML MADCLAT MCTRL ULBLK_DIS BLANK_DIS BW_SEL MBLANK SMODE
511 511 511 491 0
WDR_R WDR_G WDR_B MAX_WDR WDR_SAT
34
Micronas
ADVANCE INFORMATION
DDP 3315C
Table 3-5: XDFP Control and Status Registers in Functional Order, continued
Ref Addr. (hex) Bit Slice Min. Max. Function Default Register Name
Timing 14B 160 bit[8:0] 164 bit[8:0] 172 173 174 178 179 bit[10:0] bit[10:0] bit[10:0] bit[10:0] bit[10:0] bit[12:11] 0 0 0 0 0 0 511 1295 1295 1295 1295 1295 0 1 2 3 0 511 bit[8:0] 0 511 start point of active video relative to incoming HS signal in steps of 2 LLC2 clocks; can be used e.g. for panning vertical blanking stop last line of vertical blanking vertical blanking start first line of vertical blanking (+ 128 offset) bit[10:0] 0..1295 start of the line in respect to the pixel counter 90 < (POFS2+NEWLIN)-(3/2xSFIF)< 580 horizontal blanking start horizontal blanking stop start of dynamic focus pulse stop of dynamic focus pulse H-pulse vert. blanked H-pulse V-pulse not used Horizontal Deflection 171 17D 180 bit[0] bit[1] bit[2] bit[3] bit[4] bit[7:5] 000 001 010 100 110 181 bit[15:1] -600 600 0 0 0 0 1 1 1 1 bit[5:0] bit[9] 20 0 35 1 horizontal drive pulse duration (high time) high/low active HS input horizontal deflection control register reserved, set to "0" enable/disable vertical protection enable/disable h-safety protection disable/enable drive high during flyback start ramp up/down horizontal frequency H-Freq pixels per line @LLC 27 MHz 32 MHz in kHz 31.25 864 1024 35.1 768 912 31.46 858 1024 33.8 800 944 37.9 712 844 adjustable delay of PLL2, clamping, and blanking (relative to incoming hsync) adjust clamping pulse for analog RGB input; 1 step = 1 pixel clock adjustable delay of flyback, H/VSYNC and analog RGB (relative to PLL2) adjust horizontal drive or H/VSYNC; 1 step = 1 pixel clock proportional coefficient PLL2, c*2^-9 proportional coefficient PLL3, c*2^-9 0 0 0 0 0 0 VPROT_DIS HPROT_DIS EFLB RAMP_EN HFREQ 30 0 HDRV HSYPOL HCTRL 182 330 253 331 0 0 0 VBST NEWLIN HBST HBSO DFHB DFHE HDF 22 VBSO 0 SFIF
5
POFS2
182
bit[15:1]
-600
600
0
POFS3
183 185
bit[14:6] bit[14:6]
0 0
511 511
184 102
PKP2 PKP3
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DDP 3315C
Table 3-5: XDFP Control and Status Registers in Functional Order, continued
Ref Addr. (hex) 187 188 1EA Bit Slice Min. Max. Function
ADVANCE INFORMATION
Default
Register Name
bit[15:6] bit[15:6] bit[0] bit[1]
-512 -512 0 0
511 511 1 0 1
vertical angle vertical bow disable/enable soft stop if h-safety protection is active end of RAMP down is constant high end of RAMP down is a pulse Vertical Modes
0 0 0 0
ANGLE BOW HPROT_SS HSTOP
1E2 1E3
bit[0] bit[1:0]
0
1
VSYNC synchronized/free running raster mode
0 0
VS_MODE R_MODE
0 1 2 3 1E8 1EB bit[0] bit[0] 0 0 1 1
same input and output raster field 2 is delayed (only A raster is written) field 1 is delayed (only B raster is written) not used automatic lines-per-field adaption (constant raster amplitude) off/on disable/enable black switch off procedure on h-safety failure Vertical Parameters 0 0 VA_MODE BSO_EN
17D
bit[8]
0 1
automatic VSYNC polarity detection force VS/VS2 input low active 1 127 1023 1023 1023 VS/VS2 pin is source of VSYNC window (LPFDVSYNWIN) for sync detection lines per field number of hold lines number of flyback lines (flyback booster active)
0
VSYPOL
17D 195 196 197 198
bit[10] bit[6:0] bit[9:0] bit[9:0] bit[9:0]
0 0 0 0 0
0 32 312 10 5
VSYSRC VSYNWIN LPFD HOLDL FLYBL
Vertical Sawtooth Correction (%-values according to DAC range) 190 191 192 193 194 bit[15:8] bit[14:6] bit[15:8] bit[15:8] bit[15:8] -512 0 -512 -512 -512 511 510 511 511 511 vertical amplitude (25%) zoom (0...100...200%) vertical picture position ( 25%); (DC offset of sawtooth output). This offset is independent of EHT compensation. linearity (25%) S-correction (20%) 0 256 0 0 0 AMPL ZOOM VPOS LIN SCORR
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Micronas
ADVANCE INFORMATION
DDP 3315C
Table 3-5: XDFP Control and Status Registers in Functional Order, continued
Ref Addr. (hex) Bit Slice Min. Max. Function Default Register Name
Extreme High Tension (EHT) Compensation (%-values according to DAC range) 1AF 1B0 bit[14:6] bit[14:6] 0 1 1B1 1B2 1B3 1B4 bit[15:6] bit[15:6] bit[15:6] bit[15:6] -512 -512 -512 -512 0 2047 threshold for second coefficients of horizontal and vertical EHT compensation EHT static time constant for horizontal and vertical amplitude compensation 511 511 511 511 511 off 800 .. 0.025 ms first coefficient for static EHT compensation of vertical amplitude (100%) second coefficient for static EHT compensation of vertical amplitude (100%) first coefficient for static EHT compensation of horizontal amplitude (100%) second coefficient for static EHT compensation of horizontal amplitude (100%) East-West Parabola (%-values according to DAC range) 19A 19B 19C 19D 19E 19F 1A0 17E bit[15:7] bit[15:8] bit[15:8] bit[15:8] bit[15:8] bit[15:8] bit[15:8] bit[0] -256 -512 -512 -512 -512 -512 -512 255 511 511 511 511 511 511 0 1 picture width (0...100%) trapeze correction (50%) cushion correction (25%) upper corner correction (6%) lower corner correction (6%) upper corner correction 6th order (6%) lower corner correction 6th order (6%) use complete DAC range scale EW amplitude to linelength for PWM output 51 0 0 0 0 0 0 0 WIDTH TCORR CUSH CRNU CRNL CRNUS CRNLS EWPWMSC 0 0 0 0 EHTV_SA1 EHTV_SA2 EHTH_SA1 EHTH_SA2 2047 0 EHT_THRES EHT_STC
Micronas
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DDP 3315C
Table 3-5: XDFP Control and Status Registers in Functional Order, continued
Ref Addr. (hex) Bit Slice Min. Max. Function
ADVANCE INFORMATION
Default
Register Name
Display Frequency Doubling 17D bit[1:0] 0 1 2 3 bit[3:2] 0 1 2 3 bit[5:4] 0 1 2 3 bit[10:6] bit[11] bit[12] 0 0 0 1 1 display frequency doubling control word display raster mode (A' = field A in raster B) A A` B` B AABB A A B` B` not used minimum field length filter off 2 fields 3 fields 4 fields input sync doubling switch leave H and V sync unchanged double VSYNC and leave HSYNC unchanged double HSYNC and leave VSYNC unchanged double H and V sync reserved, set to "0" dis-/enable still picture (only available if display frequency doubling is enabled) high/low active FIFO control signals Analog RGB Insertion 116 bit[5:0] bit[8:6] 0 0 4 1 2 4 31 control signals for analog matrix reserved, set to "0" select YUV matrix RGB 480P 1080I saturation for analog RGB/YUV reserved, set to "0" 0 0 MATTYPE AMCTRL 0 0 STILL FIFOPOL 0 DFDSW 0 DFDFILT 0 DFDCTRL DFDMODE
bit[14:10] bit[15]
0 0
0 0
ASAT
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Micronas
ADVANCE INFORMATION
DDP 3315C
Table 3-5: XDFP Control and Status Registers in Functional Order, continued
Ref Addr. (hex) 1DF bit[0] bit[1] bit[2] bit[3] 0 1 bit[4] bit[5] bit[6] bit[7] bit[8] bit[9] bit[10] bit[11] bit[12] bit[15:13] 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 0 1 1 0 1 Bit Slice Min. Max. Function Default Register Name
fast blank interface mode fast blank from FBLIN1 pin force internal fast blank signal to high fast blank active high/low at FBLIN pin fast blank from FBLIN1 pin force internal fast blank signal to low fast blank priority FBLIN1>FBLIN2 FBLIN1FBLMODE FBFOH1 FBPOL FBFOL1 FBPRIO
FBFOL2 FBFOH2 FBMON CLAMP CLAMPVB HCSPOL HCSEN HCSFOH HCSLEVEL
17B 17C 17E
bit[7:0] bit[7:0] bit[9:2] bit[1]
0 0 0
255 255 255 0 1
PWM2 data word PWM1 data word PWMV data word/amplitude of parabola (if bit[1] is set) use PWMV as static PWM output use PWMV as parabola output
0 0 0 0
PWM2 PWM1 PWMV PWMVEN
Micronas
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DDP 3315C
3.3.1. Scaler Adjustment
border
ADVANCE INFORMATION
center compression
border zoom
In case of linear scaling, most of the scaler registers need not to be set. Only the scaler mode, active video length, and the fixed scaler increments (SCINC1 / SCINC2) must be written. The adjustment of the scaler for nonlinear scaling should use the parameters given in Table 3-6. An example for `panorama vision' mode is depicted in Fig. 3-4. It shows the scaling of the input signal and the variation of the scaling factor during the active video line. The scaling factor starts below 1, i.e. for the borders the video data is expanded and after it exceeds 1 it is compressed. When the picture center is reached, the scaling factor is held constant. At the second border the scaling factor changes back symmetrically.
compression 1 ratio input signal output signal
zoom
Fig. 3-4: Scaler operation for "panorama" mode
Table 3-6: Setup values for nonlinear scaler modes
Mode `waterglass' border 35% Register SCINC1 SCINC2 SCINC FFLIM SCW1 - 0 SCW1 - 1 SCW1 - 2 SCW1 - 3 SCW1 - 4 SCW2 - 0 SCW2 - 1 SCW2 - 2 SCW2 - 3 SCW2 - 4 center 3/4 1099 1024 60 715 20 156 202 338 358 20 156 384 520 540 center 5/6 1064 1024 65 717 10 123 236 349 359 10 123 417 530 540 27 MHz `panorama' border 30% center 4/3 1024 259 56 758 106 106 273 273 379 186 186 354 354 540 center 6/5 1024 407 38 796 106 106 292 292 398 177 177 363 363 540 `waterglass' border 35% center 3/4 1195 1024 54 833 51 161 256 366 417 51 161 373 483 534 center 5/6 1122 1024 42 845 37 166 257 386 423 37 166 368 497 534 32 MHz `panorama' border 30% center 4/3 1024 305 68 831 109 125 291 307 416 168 184 350 366 534 center 6/5 1024 489 46 871 126 126 310 310 436 175 175 359 359 534
40
Micronas
ADVANCE INFORMATION
DDP 3315C
4. Specifications 4.1. Outline Dimensions
0.17 0.04 64 65 41 40 15 x 0.8 = 12.0 0.1 0.8 17.2 0.15 0.37 0.04 80 1 23.2 0.15 3 0.2 24 25 1.3 0.05 2.7 0.1 0.1 20 0.1 14 0.1 23 x 0.8 = 18.4 0.1 0.8
SPGS705000-3(P80)/1E
Fig. 4-1: 80-pin Plastic Quad Flat Package (PQFP80) Weight approximately 1.61 g Dimensions in mm
4.2. Pin Connections and Short Descriptions NC = not connected LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram IN = input OUT = output SUPPLYA = analog supply pin SUPPLYD = digital supply pin Pin No.
PQFP 80-pin
Pin Name
Type
Connection
(if not used)
Short Description
1 2 3 4 5 6 7 8 9 10 11
Y6 Y7 656EN LLC2 HS VS FREQSEL CM1 CM0 VS2 XTAL2
IN IN IN IN IN IN IN IN IN IN OUT
GNDD GNDD X X X GNDD X X X GNDD X
Picture Bus Luma Picture Bus Luma (MSB) Enable 656 input mode (LLC2 = 54 MHz) System Clock Input Horizontal Sync Input Vertical Sync Input Selection of H-Drive Frequency Range Clock Select 1 Clock Select 0 Additional VSYNC input Analog Crystal Output (5-MHz Security Clock)
Micronas
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DDP 3315C
ADVANCE INFORMATION
Pin No.
PQFP 80-pin
Pin Name
Type
Connection
(if not used)
Short Description
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
XTAL1 NC GNDP VSUPP FIFORRD FIFORD FIFOWR FIFORWR PWM1 PWM2 PWMV HOUT VSTBY DFVBL HSYNC VSYNC NC ASG1 HFLB SAFETY VPROT RSW2 RSW1 SENSE GNDM VERT+ VERT- EW NC SVM ROUT
IN
X
Analog Crystal Input (5-MHz Security Clock) connect to ground GNDD
SUPPLYD SUPPLYD OUT OUT OUT OUT OUT OUT OUT OUT SUPPLYD OUT OUT OUT
X X LV LV LV LV LV LV LV X GNDP LV LV LV
Ground, Output Pin Driver Supply Voltage, Output Pin Driver FIFO Read counter Reset FIFO Read Enable FIFO Write Enable FIFO Write counter Reset I2C-controlled DAC I2C-controlled DAC I2C-controlled DAC Horizontal Drive Output Standby Supply Voltage, HOUT generation Dynamic focus blanking / horizontal DAF pulse Horizontal sync output Vertical sync output connect to ground GNDO
SUPPLYA IN IN IN OUT IN/OUT IN SUPPLYA OUT OUT OUT
X HOUT GNDO GNDO LV LV GNDO X GNDO GNDO GNDO
Analog Shield Ground Horizontal Flyback Input Safety Input Vertical Protection Input Range Switch2, Measurement ADC Range Switch1, Measurement ADC Sense ADC Input Ground, MADC Input Differential Vertical Sawtooth Output Differential Vertical Sawtooth Output East West CorrectionOutput connect to ground GNDO
OUT OUT
VSUPO VSUPO
Scan Velocity Modulation Analog Output Red
42
Micronas
ADVANCE INFORMATION
DDP 3315C
Pin No.
PQFP 80-pin
Pin Name
Type
Connection
(if not used)
Short Description
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73
GOUT BOUT GNDO XREF VSUPO VRD/BCS AGND FBLIN1 RIN1 GIN1 BIN1 FBLIN2 RIN2 / PR GIN2 / Y BIN2 / PB ASG2 HCS NC TEST RESQ SCL SDA C0 C1 C2 C3 C4 C5 C6 C7 VSUPD
OUT OUT SUPPLYA IN SUPPLYA IN SUPPLYA IN IN IN IN IN IN IN IN SUPPLYA IN
VSUPO VSUPO X X X X X GNDO GNDO GNDO GNDO GNDO GNDO GNDO GNDO X GNDD
Analog Output Green Analog Output Blue Ground, Analog Back-end Reference Input for RGB DACs Supply Voltage, Analog Back-end DAC Reference, Beam Current Safety Analog Ground for analog Matrix Fast-Blank1 Input Analog Red1 Input Analog Green1 Input Analog Blue1 Input Fast-Blank2 Input Analog Red2 / PR Input Analog Green2 / Y Input Analog Blue2 / PB Input Analog Shield Ground Half-Contrast connect to GNDO
IN IN IN/OUT IN/OUT IN IN IN IN IN IN IN IN SUPPLYD
GNDD X X X GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD X
Test Pin, connect to GNDD Reset Input, active low I2C-bus Clock I2C-bus Data Picture Bus Chroma (LSB) Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma (MSB) Supply Voltage, Digital Circuitry
Micronas
43
DDP 3315C
ADVANCE INFORMATION
Pin No.
PQFP 80-pin
Pin Name
Type
Connection
(if not used)
Short Description
74 75 76 77 78 79 80
GNDD Y0 Y1 Y2 Y3 Y4 Y5
SUPPLYD IN IN IN IN IN IN
X GNDD GNDD GNDD GNDD GNDD GNDD
Ground, Digital Circuitry Picture Bus Luma (LSB) Picture Bus Luma Picture Bus Luma Picture Bus Luma Picture Bus Luma Picture Bus Luma
4.3. Pin Descriptions Pin 3, Enable 656 mode, 656EN (Fig. 4-3) Low level selects parallel mode with LLC2 = 27/ 32 MHz, a high level selects 656 mode with LLC2=54 MHz. Pin 4, Main Clock Input, LLC2 (Fig. 4-3) This is the input for the line-locked clock signal. The frequency can be 27, 32, 40.5, 54 MHz. Pin 5, Sync Signal Input, HS (Fig. 4-3) This pin gets the horizontal sync information. Either single or double horizontal frequency or VGA horizontal sync signal. Pin 6, Sync Signal Input, VS (Fig. 4-3) This pin gets the vertical sync information. Either single or double vertical frequency or VGA vertical sync signal. Pin 7, H-Drive frequency of range select, FREQSEL (Fig. 4-3) This pin selects the frequency range for the horizontal drive signal (see Section 2.3.2. on page 16). Pin 8, Clock Select 1, CM1 (Fig. 4-3) In case of a low level on 656EN, a low level on this pin selects 27/32 MHz, a high level selects 40.5 MHz (see Section 2.3.11. on page 21). Pin 9, Clock Select 0, CM0 (Fig. 4-3) In case of a low level on 656EN, a low level on this pin selects 27 MHz, a high level selects 32 MHz (see Section 2.3.11. on page 21). Pin 10, Sync Signal Input, VS2 (Fig. 4-3) Additional pin for the vertical sync information. Via I2CRegister the used vertical sync can be switched between the inputs VS2 and VS (Pin 6) Pin 11,12, Crystal Output, Input, XTAL2 , XTAL1 (Fig. 4-15) These Pins are connected to an 5 MHz crystal oscillator. The security unit for the HOUT signal uses this clock signal as reference. Pin 14, Ground, Output Pin Driver, GNDP1) Output Pin Driver Reference Pin 15, Supply Voltage, Output Pin Driver, VSUPP1) This pin is used as supply for the following digital output pins: FIFORRD, FIFORD, FIFOWR, FIFORWR, PWM1, PWM2, PWMV, HOUT, DFVBL, HSYNC, VSYNC. Pin 16, Reset for FIFO read counter, FIFORRD (Fig. 4-4) This signal is active high and resets the read counter in the display frequency doubling FIFO. Pin 17, Read enable for FIFO, FIFORD (Fig. 4-4) This signal is active high and enables the read counter in the display frequency doubling FIFO. Pin 18, Write enable for FIFO, FIFOWR (Fig. 4-4) This signal is active high and enables the write counter in the display frequency doubling FIFO. Pin 19, Reset for FIFO write counter, FIFORWR (Fig. 4-4) This signal is active high and resets the write counter in the display frequency doubling FIFO. Pin 20, Adjustable DC Output 1, PWM1 (Fig. 4-4) This output delivers a DC voltage with a resolution of 8 bit, adjustable over the I2C bus. The output is driven by a push-pull stage. The PWM frequency is appr. 79.4 kHz. For a ripple-free voltage a first order lowpass filter with a corner frequency < 120 Hz should be applied.
44
Micronas
ADVANCE INFORMATION
DDP 3315C
Pin 33, Range Switch2 for measuring ADC, RSW2 (Fig. 4-9) These pin is a open drain pulldown output. During cutoff measurement the switch is off. During white drive measurement the switch is on. Also during the rest of time it is on. (see Section 2.2.4. on page 14). Pin 34, Range Switch1 or second input for measuring ADC, RSW1 (Fig. 4-10) These pin is a open drain pulldown output. During cutoff and white drive measurement the switch is off. During the rest of time it is on. The RSW1 pin can be used as second measurement ADC input (see Section 2.2.4. on page 14). Pin 35, Measurement ADC Input, SENSE (Fig. 4-8) This is the input of the analog to digital converter for the picture and tube measurement. Three measurement ranges are selectable with RSW1 and RSW2 (see Section 2.2.4. on page 14). Pin 36, Measurement ADC Reference Input,GNDM This is the ground reference for the measurement A/D converter. Pin 37, Vertical Sawtooth Output, VERT+ (Fig. 4-11) This pin supplies the drive signal for the vertical output stage. The drive signal is generated with 15-bit precision. The analog voltage is generated by a 4 bit current-DAC with external resistor and uses digital noise shaping. An internal pull-down resistor can be enabled by software. Pin 38, Vertical Sawtooth Output inverted, VERT- (Fig. 4-11) This pin supplies the inverted signal of VERT+. Together with this Pin it can be used to drive symmetrical deflection amplifiers. An internal pull-down resistor can be enabled by software. Pin 39, East-West Parabola Output, EW (Fig. 4-12) This pin supplies the parabola signal for the East-West correction. The drive signal is generated with 15 bit precision. The analog voltage is generated by a 4 bit current-DAC with external resistor and uses digital noise shaping. An internal pull-down resistor can be enabled by software. Pin 41, Scan Velocity Modulation Output, SVM (Fig. 4-14) This output delivers the analog SVM signal (see Section 2.1.11. on page 12). The D/A converter is a current sink like the RGB D/A converters. At zero signal the output current is 50% of the maximum output current. Pin 42, 43, 44, Analog RGB Output, ROUT, GOUT, BOUT (Fig. 4-14) This are the analog Red/Green/Blue outputs of the backend. The outputs are current sinks.
Pin 21, Adjustable DC Output 2, PWM2 (Fig. 4-4) See pin 20. Pin 22, PWMV (Fig. 4-4) This PWM output generates an adjustable vertical parabola with 7 bit resolution and appr. 79.4 kHz PWM frequency. Pin 23, Horizontal Drive, HOUT (Fig. 4-7) This open source output supplies the drive pulse for the horizontal output stage. A pulldown resistor has to be used (see Section 2.3. on page 16). Pin 24, Standby Supply Voltage, HOUT generation, VSTBY1) In standby mode, only the horizontal drive circuitry is active, regardless of RESQ (pin 62), with a duty cycle of ~79% at 55 kHz (represents the beginning of the softstart procedure). If this pin is connected to GNDP (pin 14), HOUT stays high after reset. Pin 25, DFVBL (Fig. 4-4) Blank pulse for dynamic focus during vertical blanking period, or free programmable horizontal pulse for horizontal dynamic focus generation Pin 26, HSYNC (Fig. 4-4) Horizontal sync output (in phase with the analog clamp pulse) Pin 27, VSYNC (Fig. 4-4) Vertical sync output ( interlaced or progressive) Pin 29, Shield Ground, Analog Backend, ASG11) Analog shield ground for the backend Pin 30, Horizontal Flyback Input, HFLB (Fig. 4-3) Via this pin the horizontal flyback pulse is supplied to the DDP (see Section 2.3. on page 16). Pin 31, Safety Input, SAFETY (Fig. 4-3) This input has two thresholds. A signal between the lower and upper threshold means normal function. A signal below the lower threshold or above the upper threshold is detected as malfunction and the RGB signals will be blanked. (see Section 2.3.8. on page 20). Pin 32, Vertical Protection Input, VPROT (Fig. 4-3) The vertical protection circuitry prevents the picture tube from burn-in in the event of a malfunction of the vertical deflection stage. If the peak-to-peak value of the vertical sawtooth signal is too small, the RGB output signals are blanked (see Section 2.3.8. on page 20).
Micronas
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DDP 3315C
Pin 45, Ground, Analog Backend, GNDO1) This pin has to be connected to the analog ground. No supply current for the digital stages should flow through this line. Pin 46, DAC Current Reference, XREF (Fig. 4-13) External reference resistor for DAC output currents, typical 10 k to adjust the output current of the D/A converters. (see recommended operating conditions). This resistor has to be connected to analog ground as closely as possible to the pin. Pin 47, Supply Voltage, Analog Backend, VSUPO This pin has to be connected to the analog supply voltage. No supply current for the digital stages should flow through this line. Pin 48, DAC Reference Decoupling/Beam Current Safety, VRD/BCS (Fig. 4-13) Via this pin the DAC reference voltage is decoupled by an external capacitor. The DAC output currents depend on this voltage, therefore a pulldown transistor can be used to shut off all beam currents. A decoupling capacitor of 4.7 F in parallel to 100 nF (low inductance) is required. Pin 49, Reference Ground, Analog matrix, AGND1) Analog reference ground for the analog RGB matrix Pin 50, 54, Fast Blank Input, FBLIN1/2 (Fig. 4-5) These pins are used to switch the RGB outputs to the external analog RGB inputs. FBLIN1 switches the RIN1, GIN1 and BIN1 inputs, FBLIN2 switches the RIN2, GIN2 and BIN2 inputs. The active level (low or high) can be selected by software. Pin 51, 52, 53, Analog RGB Input 1, RIN1, GIN1, BIN1 (Fig. 4-6) These pins are used to insert an external analog RGB signal, e.g. from a SCART connector which can by switched to the analog RGB outputs with the fast blank signal. Separate brightness and contrast settings for the external analog signals are provided (see Section 2.2.1. on page 13 and Fig. 2-18 on page 20). Pin 55, 56, 57, Analog RGB / YPBPR Input2, RIN2/PR, GIN2/Y, BIN2/PB (Fig. 4-6) These pins are used to insert an external analog RGB or YPBPR signal, e.g. from a SCART connector which can by switched to the analog RGB outputs with the fast blank signal. In case of YPBPR an analog HDTV RGB matrix transforms the input to RGB signals. Separate brightness and contrast settings for the external analog signals are provided (see (see Section 2.2.1. on page 13 and Fig. 2-18 on page 20). Pin 58, Shield Ground, Amalog Backend, ASG21) Analog shield ground for the backend
1)
ADVANCE INFORMATION
Pin 59, Half Contrast Input, HCS (Fig. 4-3) Via this input pin the output level of the analog RGB signals can be reduced by 6dB. Pin 61, Test Input, TEST (Fig. 4-3) This pin enables factory test modes. For normal operation it must be connected to ground. Pin 62, Reset Input, RESQ (Fig. 4-3) A low level on this pin resets the DDP 3315C. Pin 63, I2C Clock Input, SCL (Fig. 4-16)Via this pin the clock signal for the I2C-bus will be supplied. The signal can be pulled down by an internal transistor. Pin 64, I2C Data Input/Output, SDA (Fig. 4-16) Via this pin the I2C-bus data are written to or read from the DDP. Pin 65...72, Picture Bus Chroma, C0...C7 (Fig. 4-3) The Picture Bus Chroma lines carry the multiplexed color component data. For the 4:1:1 input signal (4 bit chroma) the pins C4...C7 are used. Pin 73, Supply Voltage, Digital Circuitry, VSUPD1) Pin 74, Ground, Digital Circuitry, GNDD1) Digital Circuitry Input Reference Pin 75...80, 1, 2, Picture Bus Luma, Y0...Y7 (Fig. 4-3) The Picture Bus Luma lines carry the digital luminance data. Application Note: All ground pins should be connected separately with short and low resistive lines to a central power supply ground. Accordingly all supply pins should be connected separately with short and low resistive lines to the power supply. Decoupling capacitors from VSUPP to GNDP, VSUPD to GNDD, and VSUPO to GNDO are recommended as close at possible to the pins.
1)
46
Micronas
ADVANCE INFORMATION
DDP 3315C
4.4. Pin Configuration
BIN1 FBLIN2 RIN2/PR GIN2/Y BIN2/PB ASG2 HCS NC TEST RESQ SCL SDA GIN1 RIN1 FBLIN1 AGND VRD/BCS VSUPO XREF GNDO BOUT GOUT ROUT SVM
C0 C1 C2 C3 C4 C5 C6 C7 VSUPD GNDD Y0 Y1 Y2 Y3 Y4 Y5
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 Y6 Y7 656EN LLC2 HS VS FREQSEL CM1 CM0 VS2 XTAL2 XTAL1 NC 2 3 4 5 6 7 8 9 39 38 37 36 35 34
NC EW VERTVERT+ GNDM SENSE RSW1 RSW2 VPROT SAFETY HFLB ASG1 NC VSYNC HSYNC DFVBL
DDP 3315C
33 32 31 30 29 28 27 26
25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
VSTBY HOUT PWMV PWM2 PWM1 FIFORWR FIFOWR FIFORD FIFORRD VSUPP GNDP
Fig. 4-2: PQFP80 package
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DDP 3315C
4.5. Pin Circuits VSTBY P VREF Fig. 4-3: Input pins LLC2, C[7:0], Y[7:0], HS, VS, VS2, HFLB, SAFETY, VPROT, 656EN, CM0, CM1, FREQSEL, RESQ, TEST, HCS P N VSUPP P Fig. 4-8: Input pin SENSE
ADVANCE INFORMATION
Fig. 4-7: Output pin HOUT
N GNDP Fig. 4-4: Output pins FIFORRD, FIFORD, FIFOWR, FIFORWR, DFVBL, HSYNC, VSYNC, PWM1, PWM2, PWMV N GNDM Fig. 4-9: Output pin RSW2
VSUPO P
to ADC
P N N GNDM Fig. 4-10: I/O pin RSW1
N GNDO Fig. 4-5: Analog fastblank pins FBLIN1, FBLIN2
VSUPO P/N
Clamping
P P/N P P
Flyback
VCM Fig. 4-6: Input pins RIN1, GIN1, BIN1, RIN2/PR, GIN2/Y, BIN2/PB
+
N GNDO Fig. 4-11: Output pins VERT+, VERT-
48
Micronas
ADVANCE INFORMATION
DDP 3315C
VSUPO P P P N VREF GNDD Fig. 4-16: I/O pins SCL, SDA N GNDO Fig. 4-12: Output pin EW
VRD/BCS int. ref. voltage
VSUPO
+ ref. current XREF GNDO
Fig. 4-13: Input pins XREF, VDR/BCS
N
GNDO Fig. 4-14: Output pins SVM, ROUT, GOUT, BOUT
VSTBY N
XTAL1
P
XTAL2
N P GNDD Fig. 4-15: Input pin XTAL1, Output pin XTAL2
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DDP 3315C
4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Symbol TA TS VSUP VI VI VO VGD Parameter Ambient Operating Temperature Storage Temperature Supply Voltage Input Voltage Input Voltage Output Voltage Voltage between different ground pins Pin Name All Supply Pins RESQ, SDL, SCL All other Inputs All Outputs All Ground Pins Min. 0
ADVANCE INFORMATION
Max. 65 125 6 6
VSUP(D/O)+0.3 VSUP(P/D/O)+0.3
Unit
C C
V V V V V
-40 -0.3 -0.3 -0.3 -0.3
-
0.3
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
4.6.2. Recommended Operating Conditions Symbol TA TC VSUPO VSUPP VSUPD fsys fsys Parameter Ambient Operating Temperature Case Temperature Supply Voltages, all analog Supply Pins Supply Voltages, all Output Pin Drivers Supply Voltages, all digital Supply Pins Clock Frequency with CM0 = CM1 = 656EN = GNDD Clock Frequency with CM0 = 656EN = GNDD CM1 = VSUPD Clock Frequency with CM0 = CM1 = GNDD 656EN = VSUPD RGB - DAC Current defining Resistor VSUPO VSUPP VSTBY VSUPD LLC2 LLC2 Pin Name Min. 0 0 4.75 3.15 3.15 25 29.7 Typ. 5.0 3.3 3.3 Max. 65 105 5.25 3.45 3.45 29 34.3 Unit
C C
V V V MHz MHz
fsys
LLC2
50
-
57.8
MHz
Rxref
XREF
9.5
10
10.5
k
50
Micronas
ADVANCE INFORMATION
DDP 3315C
4.6.3. Recommended Crystal Characteristics Symbol fP RR C0 CLext (see Note!) Parameter Parallel Resonance Frequency @ CL = 16 pF Series Resonance Resistance @ CL = 16 pF, fP = 5 MHz Shunt (Parallel) Capacitance External Load Capacitances (from both crystal pins connected to GNDD) Pin Name XTAL1 XTAL2 Min. Typ. 5 Max. Unit MHz
-
27
150 6 -
pF pF
Note:External capacitors at each crystal pin to ground are required. They are necessary to tune the effective load capacitance (including the capacitance of the printed circuit board and the IC package) to the required load capacitance CL of the crystal. A higher capacitance will result in a lower clock frequency. The exact value of the matching capacitor should be determined in the actual application (PCB layout). CLext = 2 (CL - CPCB - CPACK)
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DDP 3315C
4.6.4. Characteristics
ADVANCE INFORMATION
Min./Max. values at TA = 0 to 65 C, VSUP(P/D) = 3.15 to 3.45 V, VSUPO = 4.75 to 5.25 V, f = 27 MHz Typical values at: TC = 70 C, VSUP(P/D) = 3.3 V, VSUPO = 5 V, f = 27 MHz all values with Rxref = 10 k 4.6.4.1. General Characteristics Symbol PTOT IVSUPO IVSUPD IVSUPP IVSTBY IL Parameter Total Power Dissipation Current Consumption Analog Backend Current Consumption Digital Processing Current Consumption Output Pin Driver Current Consumption horizontal drive generation Input and Output Leakage Current (if not otherwise specified) VSUPO VSUPD VSUPP VSTBY Pin Name Min. 1 Typ. 0.750 100 70 2 0.4 Max. 1.0 tbd tbd tbd 1 Unit W mA mA mA mA
A
4.6.4.2. LLC2: Line-locked Clock Input
Symbol VIL VIH tR, tF CIN 1/TLLC2 tWL2 tWH2 Parameter Input Low Voltage Input High Voltage Clock Rise / Fall Time Input Capacitance Clock Frequency Clock Low Time Clock High Time Pin Name LLC2 Min. 2.0 12.5 tbd tbd Typ. 5 Max. 0.8 TLLC2/ 4 56.7 Unit V V ns pF MHz ns ns Test Conditions
52
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ADVANCE INFORMATION
DDP 3315C
4.6.4.3. Luma, Chroma Inputs
Symbol VIL VIH tIS tIH CIN Parameter Input Low Voltage Input High Voltage Input Setup Time Input Hold Time Input Capacitance Pin Name Y[0...7] C[0...7] HS VS VS2 Min. 2.0 4 4 Typ. 5 Max. 0.8 Unit V V ns ns pF Test Conditions
TLLC2 tWH2 LLC2 tWL2 VIH VIL tR2 tF2 tIS Y,C Inputs tIH VIH VIL
Fig. 4-17: Line-locked clock input pins and luma / chroma bus input timing
4.6.4.4. Digital Inputs, Static Pins
Symbol VIL VIH CIN Parameter Input Low Voltage Input High Voltage Input Capacitance Pin Name HCS RESQ TEST CM0 CM1 656EN FREQSEL Min. 2.0 Typ. 5 Max. 0.8 Unit V V pF Test Conditions
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DDP 3315C
4.6.4.5. I2C-Bus Interface
Symbol VIL VIH VOL IOL CIN tF tR fSCL tLOW tHIGH tIS tIH tOD tOH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output Low Current Input Capacitance Signal Fall Time Signal Rise Time Clock Frequency Low Period of SCL High Period of SCL Input data Set Up Time to SCL high Input data Hold Time to SCL low Output data Delay Time to SCL high Output data Hold Time to SCL low SDA SCL Pin Name SDA SCL Min. 2.0 0 1.3 0.6 55 55 tbd 15 Typ. 900 Max. 0.8 0.6 10 5 300 300 400 Unit V V V mA pF ns ns kHz s s ns ns ns ns
ADVANCE INFORMATION
Test Conditions
IOL = 6 mA
CL = 400 pF CL = 400 pF
1/fSCL tHIGH SCL tR tIS SDA as input tOD tOH SDA as output tF tIS VIH VIL VIH VIL tLOW VIH VIL
Fig. 4-18: I2C bus timing
54
Micronas
ADVANCE INFORMATION
DDP 3315C
4.6.4.6. Horizontal Flyback Input
Symbol VIL VIH VIMAX VIHST Parameter Input Low Voltage Input High Voltage Maximum Input Voltage Input Hysteresis 0.2 Pin Name HFLB Min. 2.5 Typ. Max. 1.9 VSUPO +0.3 Unit V V V V maximum clamping current ~10mA average Test Conditions
4.6.4.7. Sync Signals and PWM Outputs
Symbol VOL VOH tOT IOL Parameter Output Low Voltage Pin Name FIFORRD FIFORD FIFORWR FIFOWR DFVBL HSYNC VSYNV PWM1 PWM2 PWMV Min. Typ. Max. 0.4 Unit V Test Conditions IOL = 1.6 mA I2C[PSTFFC] = 6
VSUPP - 0.4
Output High Voltage
-
VSUPP
V
-IOL = 1.6 mA I2C[PSTFFC] = 6 CLOAD = 30 pF I2C[PSTFFC] = 6
Output Transition Time
-10
10
20
ns
Output Current
-
10
mA
4.6.4.8. Horizontal Drive Output
Symbol VOL VOH tOF IOH Parameter Output Low Voltage Output High Voltage (Open Source Stage) Output Fall Time Output High Current Pin Name HOUT Min. Typ. tbd 60 Max. VSTB Y Unit V V ns mA CLOAD = 30pF Test Conditions external pull-down resistor
4.6.4.9. Vertical Protection Input
Symbol VIA VIB VIMAX VIHST Parameter Input Threshold A Input Threshold B Maximum Input Voltage Input Hysteresis A and B 0.1 Pin Name VPROT Min. Typ. 1.0 1.5 VSUPO +0.3 Max. Unit V V V V maximum clamping current ~10 mA average Test Conditions
Micronas
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DDP 3315C
4.6.4.10. Horizontal Safety Input
Symbol VIA VIB VIMAX VIHST Parameter Input Threshold A Input Threshold B Maximum Input Voltage Input Hysteresis A and B 0.1 Pin Name SAFETY Min. Typ. 2.2 3.4
VSUPO +0.3
ADVANCE INFORMATION
Max.
Unit V V V V
Test Conditions
maximum clamping current ~10 mA average
-
4.6.4.11. Vertical and East/West D/A Converter Output
Symbol Parameter Resolution VOMIN VOMAX IDACN PSRR Minimum Output Voltage Maximum Output Voltage Full scale DAC Output Current Power Supply Rejection Ratio Pin Name EW VERT+ VERT- Min. 2.82 415 Typ. 15 0 3 440 20 Max. 3.2 465 Unit bit V V A dB Rload = 6.8 k Rxref = 10 k Rload = 6.8 k Rxref = 10 k Rxref = 10 k Test Conditions
4.6.4.12. East/West PWM Output
Symbol VOL Parameter Output Low Voltage Pin Name EW Min. Typ. Max. 0.4 Unit V Test Conditions IOL = 1.6 mA I2C[PSTEW] = 6 VOH Output High Voltage
VSUPO - 0.4
-
VSUPO
V
-IOL = 1.6 mA I2C[PSTPWEW] = 6
tOT
Output Transition Time
-
tbd
ns
CLOAD = 10 pF Rlp = 4.7 k Clp = 100 nF I2C[PSTPEW] = 6
4.6.4.13. Sense A/D Converter Input
Symbol VI511 C0 RI Parameter Input Voltage for code 511 Digital Output for zero Input Input Impedance Pin Name SENSE RSW1 Min. 1 Typ. 2.6 Max. 16 Unit V LSB M Test Conditions
Range Switch Outputs RON IMax ILEAK Output On Resistance Maximum Current Leakage Current RSW1 RSW2 50 15 600 mA nA RSW High Impedance IOL = 10 mA
56
Micronas
ADVANCE INFORMATION
DDP 3315C
4.6.4.14. Analog RGB / YPBPR and FB Inputs
Symbol VRGBINPP ILSB VRGBIN Parameter nominal RGB Input Voltage peak-to-peak minimum current step size RGB Input Voltage for Maximum Output Current Pin Name RIN1 GIN1 BIN1 RIN2/PR GIN2/Y BIN2/PB Min. 0.5 3.13 CRGBIN tc CIN IIL VINOFF VRGBINMAX VCLAMP IICMAX VCLIP VRGBINMAX VCLAMP IICMAX VCLIP VFBLOFF VFBLON VFBLTRIG tPID External RGB Input Coupling Capacitor Clamp Pulse Width Input Capacitance Input Leakage Current Offset Voltage Absolute Maximum External RGB Input Voltage Range Clamp Level at Input Maximum clamp current during tc RGB Input Voltage for Clipping Current Absolute Maximum External RGB Input Voltage Range Clamp Level at Input Maximum clamp current during tc RGB Input Voltage for Clipping Current FBLIN Low Level FBLIN High Level Fast Blanking Trigger Level typical Delay Fast Blanking to RGBOUT from midst of FBLIN-transition to 90% of RGBOUT- transition FBLIN1 FBLIN2 RIN2/PR GIN2/Y BIN2/PB -1.5 1.6 RIN1 GIN1 BIN1 -0.5 -10 -0.3 0.2 1.4 2.3 -3 0.9 1.4 0.7 8 3 0.5 15 ns Internal RGB = 3.75 mA Full Scale Int. Brightness = 0 External Brightness = 1.5 mA (Full Scale) RGBin = 0 VFBLOFF = 0.4 V VFBLON = 1.0 V Rise and fall time = 2 ns 1.5 3.5 Typ. 0.7 4.4 0.5 0.7 1.0 15 1.6 tbd 0.5 10 1.4 Max. 1.0 6.25 nF s pF A mV V V mA V V V mA V V V at Pin Clamping ON Clamping ON at Pin Clamping ON Clamping ON Clamping OFF, VIN = -0.3...3.5 V Unit VPP A Contrast setting: tbd Contrast setting: tbd Contrast setting: tbd Test Conditions SCART Spec: 0.7 V 3 dB
Difference of Internal Delay to External RGBin Delay Switch-Over-Glitch
-5 -
0.5
+5 -
ns pAs Switch from 3.75 mA (int) to 1.5 mA (ext)
Micronas
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DDP 3315C
4.6.4.15. Analog RGB Outputs, D/A Converters
Symbol Parameter Pin Name Min. Typ. Max. Unit
ADVANCE INFORMATION
Test Conditions
Internal RGB Signal D/A Converter Characteristics Resolution IFS DNL INL trs SNR Full Scale Output Current Differential Nonlinearity Integral Nonlinearity Rise and Fall Time Signal to Noise RGB Gain Match R/B/G Crosstalk from any 2 to the 3rd Crosstalk from external RGB to main RGB from any 3 to the 4th Internal RGB Brightness D/A Converter Characteristics Resolution IFS IFS DNL INL Full Scale Output Current relative Full Scale Output Current absolute Differential Nonlinearity Integral Nonlinearity RGB Gain Match External RGB gain match to main RGB RGB Output Cutoff D/A Converter Characteristics Resolution IFS IFS DNL INL Full Scale Output Current relative Full Scale Output Current absolute Differential nonlinearity Integral nonlinearity External RGB gain match to main RGB ROUT GOUT BOUT 58.8 -2 9 60 2.25 61.2 1 2 2 bit % mA LSB LSB % R-R, G-G, B-B Ref to max. digital RGB ROUT GOUT BOUT 39.2 -2 -2 9 40 1.5 40.8 1 2 2 2 bit % mA LSB LSB % % R-G, R-B, G-B R-R, G-G, B-B Ref to max. digital RGB ROUT GOUT BOUT 3.6 +50 -2 10 3.75 3 3.9 1 2 2 -46 bit mA LSB LSB ns dB % dB 10% to 90%, 90% to 10% Signal: 1 MHz full scale Bandwidth: 10 MHz R-G, R-B, G-B Passive channel: IOUT = 1.88 mA Crosstalk-Signal: 7 MHz, 3 mAPP Rref = 10 k
-
-
-50
dB
58
Micronas
ADVANCE INFORMATION
DDP 3315C
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
RGB Output Ultrablack D/A Converter Characteristics Resolution IFS Full Scale Output Current relative Full Scale Output Current absolute ROUT GOUT BOUT 19.6 1 20 0.75 20.4 bit % mA Ref to max. digital RGB
External RGB / YPBPR Voltage/Current Converter Characteristics Resolution IFS Full Scale Output Current relative Full Scale Output Current absolute CR Contrast Adjust Range RGB Gain Match -2 ROUT GOUT BOUT 96 11 100 104 bit % Ref. to max. Digital RGB VIN = 0.7 VPP, contrast = 1800 Ref. to max. Digital RGB VIN = 0.7 VPP, contrast = 1800
-
3.75
-
mA
0:2047 -
2 % Measured at RGB Outputs VIN = 0.7 V, contrast = 1800 Passive channel: VIN = 0.7 V, contrast = 1800 Crosstalk signal: 7 MHz, 3 mAPP
R/B/G Crosstalk from any 2 to the 3rd
-
-
-46
dB
RGB Crosstalk from main RGB from any 3 to the 4th RGB Input Noise and Distortion RGB Input Bandwidth -3dB RGB Input THD
-
-
-50
dB
25 -
-
-50 -50 -40
dB MHz dB dB LSB LSB
VIN = 0.7 VPP at 7 MHz Bandwidth: 10 MHz VIN = 0.7 VPP, Input signal 1 MHz Input signal 7 MHz VIN = 0.7 VPP VIN = 0.7 V
Differential Nonlinearity of Contrast Adjust Integral Nonlinearity of Contrast Adjust
-
1.0 7
Micronas
59
DDP 3315C
ADVANCE INFORMATION
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
External RGB Brightness D/A Converter Characteristics Resolution ROUT GOUT BOUT 9 bit
IEXBR
Full Scale Output Current relative Full Scale Output Current absolute Differential Nonlinearity Integral Nonlinearity RGB Gain Match
39.2 -2
40 1.5 -
40.8 1 2 2
% mA LSB LSB %
Ref to max. digital RGB
R-G, R-B, G-B
Analog RGB output Pins VRGBO IMAX R,G,B Output Voltage Maximum output current ROUT GOUT BOUT -1.0 8.25 0.3 V mA Referred to VSUPO All DAC with full scale
4.6.4.16. Scan Velocity Modulation Output
Symbol Parameter Resolution IOUT IOUT IOUT IOUT Full Scale Output Current Differential Nonlinearity Integral Nonlinearity Glitch Pulse Charge Pin Name SVMOUT Min. 1.55 Typ. 8 1.875 0.5 Max. 2.25 0.5 1 Unit bit mA LSB LSB pAs Ramp, output line is terminated on both ends with 50 10% to 90%, 90% to 10% Test Conditions
IOUT
Rise and Fall Time
-
3
-
ns
4.6.4.17. DAC Reference, Beam Current Safety
Symbol VDACREF Parameter DAC-Ref. Voltage DAC-Ref. Output resistance VXREF DAC-Ref. Voltage Bias Current Generation Pin Name VRD/BCS VRD/BCS XREF Min. 2.38 18 2.3 Typ. 2.50 25 2.5 Max. 2.67 32 2.7 Unit V k V Rxref = 10 k Test Conditions
60
Micronas
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DDP 3315C
61
DDP 3315C
6. Data Sheet History 1. Advance Information: "DDP 3315C Display and Deflection Processor", Dec. 5, 2001, 6251-521-1AI. First release of the advance information.
ADVANCE INFORMATION
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-521-1AI
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
62
Micronas

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